Nirvan007 / Analog_Electronics

Related projects ⓘ

Alternatives and complementary repositories for Analog_Electronics

• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆16Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆26Updated 4 years ago
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆98Updated 2 years ago
• KOTHAVANI / 100-Days-of-RTL-code
  ☆40Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆29Updated last year
• semiDESIgner / 50daysRTLcode
  ☆16Updated last year
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆17Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆48Updated 2 years ago
• Artityagi123456789 / 100DaysofRTL
  ☆13Updated 8 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆135Updated 2 months ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated 9 months ago
• Ummidichandrika / 100-Days-of-RTL
  ☆99Updated 10 months ago
• Artityagi123456789 / 15DaysofUVM
  ☆12Updated 9 months ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆113Updated 11 months ago
• Prajwal-ECE / RTL-Coding
  ☆9Updated last year
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• asinghani / open-eda-course
  ☆52Updated last year
• vsdip / vsdsram_sky130
  ☆39Updated 2 years ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆26Updated 7 months ago
• Prananya123 / RTL-Coding
  ☆22Updated last year
• shubhi704 / APB-Protocol
  ☆36Updated 3 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆14Updated last year
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆27Updated 2 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆21Updated 3 years ago
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆23Updated 2 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆19Updated 3 years ago
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆13Updated 3 years ago