ronak66 / Direct-Mapped-CacheLinks
Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line
☆14Updated 7 years ago
Alternatives and similar repositories for Direct-Mapped-Cache
Users that are interested in Direct-Mapped-Cache are comparing it to the libraries listed below
Sorting:
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- A Verilog implementation of a processor cache.☆34Updated 8 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆33Updated 2 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- BlackParrot on Zynq☆48Updated this week
- Parameterized Booth Multiplier in Verilog 2001☆51Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- ☆40Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- A verilog implementation for Network-on-Chip☆81Updated 7 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆20Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- Verilog RTL Design☆46Updated 4 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 3 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆39Updated last year
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago