ash-olakangal / RISC-V-Processor
Verilog implementation of multi-stage 32-bit RISC-V processor
☆88Updated 4 years ago
Alternatives and similar repositories for RISC-V-Processor:
Users that are interested in RISC-V-Processor are comparing it to the libraries listed below
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆80Updated last year
- Basic RISC-V Test SoC☆112Updated 5 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆33Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆71Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆225Updated 6 months ago
- 32 bit RISC-V CPU implementation in Verilog☆27Updated 3 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆120Updated 3 years ago
- SystemVerilog Tutorial☆123Updated this week
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆105Updated last year
- This repo provide an index of VLSI content creators and their materials☆141Updated 6 months ago
- Simple 8-bit UART realization on Verilog HDL.☆97Updated 9 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆38Updated 7 months ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆56Updated 3 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆119Updated 6 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- A simple RISC V core for teaching☆176Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆123Updated 5 years ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆73Updated 9 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆64Updated last year
- ☆72Updated 5 months ago
- RISC-V 32-bit microcontroller developed in Verilog☆167Updated 4 months ago
- ☆130Updated 2 years ago