Verilog implementation of multi-stage 32-bit RISC-V processor
☆163Nov 2, 2020Updated 5 years ago
Alternatives and similar repositories for RISC-V-Processor
Users that are interested in RISC-V-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- opensource EDA tool flor VLSI design☆36Sep 17, 2023Updated 2 years ago
- A web-based graphical simulator of a simple 32-bit, single-cycle implementation of RISC-V☆26Mar 16, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆365Jan 12, 2018Updated 8 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- RISC-V CPU Core (RV32IM)☆1,719Sep 18, 2021Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆29Jul 23, 2023Updated 2 years ago
- RV64IMAC modelling using System Verilog HDL☆25Aug 10, 2024Updated last year
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A Verilog RTL model of a simple 8-bit RISC processor☆21Jan 15, 2019Updated 7 years ago
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆12Apr 21, 2024Updated 2 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- A simple RISC-V CPU written in Verilog.☆70Mar 16, 2026Updated 2 months ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆149Jul 17, 2022Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- APB master and slave developed in RTL.☆25Oct 25, 2025Updated 6 months ago
- Custom 64-bit pipelined RISC processor☆18Dec 8, 2025Updated 5 months ago
- Collection of simple interfaces for Digilent Pmods☆12Aug 3, 2023Updated 2 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- Simple cache design implementation in verilog☆55Nov 20, 2023Updated 2 years ago
- ☆13May 8, 2023Updated 3 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆26Feb 24, 2026Updated 3 months ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated last year
- ☆16Mar 27, 2024Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆64Jul 5, 2024Updated last year
- Image Processing Toolbox in Verilog using Basys3 FPGA☆232May 20, 2025Updated last year
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆41Apr 13, 2021Updated 5 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago