MatejGomboc / Verilog-I2S-TranscieverLinks
I2S transciever implemented in Verilog HDL
☆32Updated 8 years ago
Alternatives and similar repositories for Verilog-I2S-Transciever
Users that are interested in Verilog-I2S-Transciever are comparing it to the libraries listed below
Sorting:
- Audio controller (I2S, SPDIF, DAC)☆90Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆79Updated 4 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆59Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆113Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- Wishbone controlled I2C controllers☆55Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆66Updated last year
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- Delta Sigma DAC FPGA☆44Updated 9 months ago
- A series of CORDIC related projects☆117Updated last year
- ULPI Link Wrapper (USB Phy Interface)☆32Updated 5 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆122Updated 4 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Updated 3 years ago
- USB Full Speed PHY☆47Updated 5 years ago
- USB 2.0 Device IP Core☆71Updated 8 years ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Updated 5 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- MIPI DSI controller☆79Updated 3 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆45Updated 4 years ago
- Verilog wishbone components☆123Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆69Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆61Updated 2 years ago