Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algorithms have been proposed over the last couple of decades to reduce the number of computations and memory requirements involved in the DCT computation algorithm. One of the algorithms is implemented here using V…
☆26May 5, 2015Updated 10 years ago
Alternatives and similar repositories for 8PointDCT_Verilog
Users that are interested in 8PointDCT_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- 2D discrete cosine transform (DCT) of an 8x8 image in verilog HDL☆16Sep 2, 2022Updated 3 years ago
- Take parameters of LeNet from caffe as a pre-trained model.☆12Jun 15, 2016Updated 9 years ago
- AES-based-on-FPGA developed by verilog.☆23Apr 23, 2020Updated 5 years ago
- Implementation of Sobel Filter in Verilog☆25Mar 10, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆10Mar 18, 2020Updated 6 years ago
- Autocorrelation and cross-correlation signal☆11Oct 19, 2020Updated 5 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- This repository contains FPGA code for various projects like Lighthouse Tracking as well as some IP cores. The repository is board-indepe…☆14Sep 8, 2021Updated 4 years ago
- Simple sram controller in verilog.☆36Jun 5, 2016Updated 9 years ago
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆10Mar 18, 2014Updated 12 years ago
- I2S transciever implemented in Verilog HDL☆32Oct 11, 2017Updated 8 years ago
- ☆15Jan 9, 2022Updated 4 years ago
- Display ov7670 camera video on VGA monitors through Video DMA on ZedBoard☆19Jun 20, 2017Updated 8 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- An i2c master controller implemented in Verilog☆33Jul 26, 2017Updated 8 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆14May 3, 2012Updated 13 years ago
- Simple AlexNet forward path implementation in Matlab☆25Nov 8, 2021Updated 4 years ago
- This page contains supplementary material for our paper entitled "COMPLEXITY ANALYSIS OF NEXT-GENERATION VVC ENCODING AND DECODING"☆18May 22, 2020Updated 5 years ago
- Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog☆20Jul 21, 2015Updated 10 years ago
- mirror of git://source.ffmpeg.org/ffmpeg.git☆26Updated this week
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆31Nov 3, 2025Updated 4 months ago
- ☆18Oct 3, 2016Updated 9 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- SPI interface connect to APB BUS with Verilog HDL☆40Jun 27, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ☆13Jan 28, 2026Updated last month
- JPEG Compression using DCT (Discrete Cosine Transform) and DWT (Discrete Wavelet Transform) in Matlab.☆10Nov 26, 2019Updated 6 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆15Feb 17, 2019Updated 7 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- 基于hanny的友情链接插件做修改,使其在Material Theme中保持原有风格☆11Sep 23, 2017Updated 8 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- A very simple VGA controller written in verilog☆25Jun 1, 2012Updated 13 years ago