Master and Slave made using AMBA AXI4 Lite protocol.
☆32Oct 9, 2020Updated 5 years ago
Alternatives and similar repositories for AMBA-AXI4-Lite
Users that are interested in AMBA-AXI4-Lite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆147May 14, 2021Updated 5 years ago
- ☆15May 8, 2018Updated 8 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆14Aug 1, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 months ago
- ☆16Apr 21, 2019Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆36Feb 7, 2025Updated last year
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆50May 10, 2024Updated 2 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆15Jun 28, 2021Updated 5 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 4 years ago
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 11 years ago
- 我的一生一芯项目☆16Dec 14, 2021Updated 4 years ago
- ☆13Apr 1, 2017Updated 9 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- AXI Interconnect☆58Aug 20, 2021Updated 4 years ago
- General purpose IO port with AXI4-Lite interface☆10Feb 7, 2025Updated last year
- ☆18Apr 5, 2015Updated 11 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This course walks you through the Linux OS commands and usage.☆21Sep 26, 2022Updated 3 years ago
- A VHDL implementation of an AXI4 Master☆16Nov 7, 2017Updated 8 years ago
- SDRAM controller with AXI4 interface☆107Aug 8, 2019Updated 6 years ago
- A boilerplate for a freeCodeCamp project.☆20Jun 3, 2024Updated 2 years ago
- 在FPGA端实现JPEG编码(开发中……☆13Oct 17, 2024Updated last year
- 一生一芯项目☆19Oct 28, 2023Updated 2 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆54Jul 4, 2020Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆19Aug 3, 2021Updated 4 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆12Jun 14, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- uvm AXI BFM(bus functional model)☆271Jun 23, 2013Updated 13 years ago
- General Purpose AXI Direct Memory Access☆78May 12, 2024Updated 2 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- FPGA based MIDI keyboard project for EEE 304 (Digital Electronics Laboratory)☆14Sep 21, 2022Updated 3 years ago
- UVM examples☆14May 1, 2015Updated 11 years ago
- SKILL Codes, PCell Creation☆21May 21, 2021Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago