somyadashora / AMBA-AXI4-Lite
Master and Slave made using AMBA AXI4 Lite protocol.
☆26Updated 4 years ago
Alternatives and similar repositories for AMBA-AXI4-Lite:
Users that are interested in AMBA-AXI4-Lite are comparing it to the libraries listed below
- AXI Interconnect☆47Updated 3 years ago
- Verification IP for APB protocol☆57Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆33Updated 7 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆41Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆44Updated 11 months ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- ☆18Updated 2 years ago
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆83Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- ☆36Updated 9 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- Sample UVM code for axi ram dut☆31Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 9 months ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- ☆39Updated 3 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- UVM Generator☆44Updated 9 months ago
- ☆25Updated 3 years ago