somyadashora / AMBA-AXI4-LiteLinks
Master and Slave made using AMBA AXI4 Lite protocol.
☆29Updated 5 years ago
Alternatives and similar repositories for AMBA-AXI4-Lite
Users that are interested in AMBA-AXI4-Lite are comparing it to the libraries listed below
Sorting:
- AXI Interconnect☆54Updated 4 years ago
- Verification IP for APB protocol☆72Updated 5 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆102Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆93Updated last year
- UART design in SV and verification using UVM and SV☆51Updated 6 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆133Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆71Updated last year
- ☆52Updated 4 years ago
- AXI4 BFM in Verilog☆35Updated 9 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆52Updated 5 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆31Updated 10 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- VIP for AXI Protocol☆160Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆18Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆57Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆42Updated last year
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Updated 5 years ago
- ☆26Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆20Updated 3 years ago