Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
☆25Jun 5, 2018Updated 7 years ago
Alternatives and similar repositories for verilog-book
Users that are interested in verilog-book are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- example code for the logi-boards from pong chu HDL book☆30Sep 4, 2015Updated 10 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆63Nov 25, 2020Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- Making Lattice SensAI work properly on tinyVision products☆12Nov 22, 2022Updated 3 years ago
- ☆19Oct 20, 2025Updated 5 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Netlist and Verilog Haskell Package☆19Nov 21, 2010Updated 15 years ago
- The Orange Cartridge, an FPGA cartridge for the C64/C128☆20Sep 24, 2023Updated 2 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆37Jan 10, 2019Updated 7 years ago
- FPGA clone of the game Super Hexagon☆12May 12, 2015Updated 10 years ago
- IceCore Ice40 HX based modular core☆47Jan 23, 2021Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- All About HDL☆39Aug 21, 2019Updated 6 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Eagle files for a STM32F4-DISCOVERY breakout board.☆11Oct 16, 2015Updated 10 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- This a a Diagnostics Harness for the Commodore VIC-20.☆25Jul 26, 2023Updated 2 years ago
- Brendan's repo for interesting SQL☆13Feb 27, 2020Updated 6 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 2 years ago
- CodeChef Code☆10Updated this week
- All of my Verilog_HDL codes☆11Apr 5, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- ☆11Jul 26, 2017Updated 8 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- PSA-ADAC SDC-600 Secure Debug Manager library for authenticated debug☆15Mar 18, 2025Updated last year
- FPU Double VHDL☆12Jul 17, 2014Updated 11 years ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated last month
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆15Feb 17, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Knowledge Graph of FPGA☆14Aug 21, 2021Updated 4 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- Sources of Tuned Simons' Basic☆41Feb 28, 2026Updated last month
- A very simple VGA controller written in verilog☆25Jun 1, 2012Updated 13 years ago
- BlackIceMx - Core Module carrier with MixMods/Pmod interfaces☆17Sep 2, 2019Updated 6 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 6 months ago
- DEC VAX-11/750 CPU RTL Model☆16Nov 24, 2025Updated 4 months ago