Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
☆25Jun 5, 2018Updated 8 years ago
Alternatives and similar repositories for verilog-book
Users that are interested in verilog-book are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆68Nov 25, 2020Updated 5 years ago
- FPGA Games Gathered from GitHub in one place☆23Aug 19, 2022Updated 4 years ago
- Arduino DSKx / 32K / FTP / NTP shield for the TI99/4a☆18Jun 10, 2025Updated last year
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- All About HDL☆40Aug 21, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Making Lattice SensAI work properly on tinyVision products☆13Nov 22, 2022Updated 3 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- Xilinx Unisim Library in Verilog☆93Jul 22, 2020Updated 6 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- rv6 is a kernel & operating system written entirely in rust.☆11Nov 7, 2019Updated 6 years ago
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆32Aug 15, 2025Updated last year
- The Orange Cartridge, an FPGA cartridge for the C64/C128☆21Sep 24, 2023Updated 3 years ago
- A machine learning application to read/classifiy AD5933 data from the MEMS Cancer sensor☆12Dec 11, 2024Updated last year
- C64 core☆14Jul 25, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- All the projects and assignments done as part of VLSI course.☆21Sep 23, 2020Updated 6 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- FPGA clone of the game Super Hexagon☆12May 12, 2015Updated 11 years ago
- IceCore Ice40 HX based modular core☆46Jan 23, 2021Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 13 years ago
- FPU Double VHDL☆12Jul 17, 2014Updated 12 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Examples of unions, interfaces, and assertions in SystemVerilog☆14Aug 31, 2013Updated 13 years ago
- RMII Firewall FPGA☆25Dec 2, 2019Updated 6 years ago
- Eagle files for a STM32F4-DISCOVERY breakout board.☆11Oct 16, 2015Updated 11 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆54Feb 22, 2022Updated 4 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆16Feb 17, 2019Updated 7 years ago
- Knowledge Graph of FPGA☆14Aug 21, 2021Updated 5 years ago
- This a a Diagnostics Harness for the Commodore VIC-20.☆27Jul 26, 2023Updated 3 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆16Mar 27, 2024Updated 2 years ago
- ☆10Aug 19, 2018Updated 8 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- repository for binary releases☆26Jul 30, 2026Updated 2 months ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago