adibis / Interrupt_ControllerLinks
An 8 input interrupt controller written in Verilog.
☆28Updated 13 years ago
Alternatives and similar repositories for Interrupt_Controller
Users that are interested in Interrupt_Controller are comparing it to the libraries listed below
Sorting:
- ☆20Updated 3 years ago
- ☆17Updated 10 years ago
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆31Updated 10 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- AXI Interconnect☆54Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆17Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Structured UVM Course☆54Updated last year
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 6 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆18Updated 2 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- Maven Silicon Project☆19Updated 7 years ago
- AMBA 3 AHB UVM TB☆34Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- Asynchronous fifo in verilog☆37Updated 9 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- ☆26Updated 4 years ago
- my UVM training projects☆37Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆71Updated last year
- SystemVerilog examples and projects☆20Updated 6 months ago
- ☆52Updated 4 years ago
- Verification IP for APB protocol☆72Updated 5 years ago
- A complete UVM TB for verification of single port 64KB RAM☆16Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- System on Chip verified with UVM/OSVVM/FV☆32Updated 2 weeks ago