Alternatives and similar repositories for usb_system

Users that are interested in usb_system are comparing it to the libraries listed below

• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆29Updated 5 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆59Updated 2 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆94Updated 5 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated this week
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• sam210723 / fpga
  Collection of projects for various FPGA development boards
  ☆46Updated last year
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 4 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆59Updated 9 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆62Updated 6 years ago
• AngeloJacobo / ULX3S_FPGA_Camera_Streaming
  Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
  ☆23Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆29Updated 6 months ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆29Updated 5 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆28Updated 4 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated 2 months ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 6 years ago
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆16Updated 2 years ago
• StereoNinja / StereoNinjaFPGA
  Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board
  ☆31Updated 2 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• ZipCPU / wbspi
  A collection of SPI related cores
  ☆17Updated 10 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 11 months ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆41Updated 5 years ago
• kazkojima / lunauac2-pdm
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆16Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 6 months ago