☆17Apr 19, 2026Updated 6 months ago
Alternatives and similar repositories for MLCAD25-Contest-Scripts-Benchmarks
Users that are interested in MLCAD25-Contest-Scripts-Benchmarks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆48Apr 10, 2026Updated 6 months ago
- GPU-accelerated RePlAce☆14Jun 11, 2024Updated 2 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆55Jan 19, 2025Updated last year
- ☆28Nov 7, 2024Updated last year
- FastPoly: An Efficient Polynomial Package for the Verification of Integer Arithmetic Circuits☆14Aug 5, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- OpenDesign Flow Database☆17Oct 31, 2018Updated 8 years ago
- ☆11Feb 25, 2023Updated 3 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆16Mar 12, 2023Updated 3 years ago
- ☆31Apr 23, 2024Updated 2 years ago
- ☆13Oct 17, 2026Updated 2 weeks ago
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆23May 2, 2026Updated 5 months ago
- ☆15Jul 25, 2024Updated 2 years ago
- ☆10Jan 19, 2024Updated 2 years ago
- ☆32Oct 12, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- ☆13Mar 3, 2025Updated last year
- ☆13Mar 7, 2024Updated 2 years ago
- ☆11Apr 8, 2025Updated last year
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆42May 17, 2024Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆45Apr 13, 2025Updated last year
- The SoC used for the beta phase of Hack@DAC 2018.☆17May 14, 2020Updated 6 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆33Feb 11, 2026Updated 8 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Hack@DAC 2021☆21Jul 24, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆54May 29, 2025Updated last year
- A standalone structural (gate-level) verilog parser☆43Oct 12, 2026Updated 2 weeks ago
- ☆16Apr 8, 2023Updated 3 years ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- ☆62Oct 10, 2026Updated 3 weeks ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆32Jun 23, 2025Updated last year
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆356Sep 30, 2026Updated last month
- ☆23May 25, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Lean-embedded framework to verify Verilog modules☆17Oct 6, 2026Updated 3 weeks ago
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- Parasitic capacitance analysis of foundry metal stackups☆21Jan 12, 2026Updated 9 months ago
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆37Jun 17, 2026Updated 4 months ago
- ☆102Jun 24, 2025Updated last year
- Hardware Description Library☆96Feb 17, 2026Updated 8 months ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago