CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
☆1,291Aug 26, 2026Updated 3 weeks ago
Alternatives and similar repositories for cv32e40p
Users that are interested in cv32e40p are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,060Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,120Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆720Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,001Nov 15, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆279Nov 6, 2024Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆497May 8, 2026Updated 4 months ago
- An open-source microcontroller system based on RISC-V☆1,066Feb 6, 2024Updated 2 years ago
- VeeR EH1 core☆967Jul 16, 2026Updated 2 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 8 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,700Updated this week
- RISC-V CPU Core☆449Jun 24, 2025Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,384Sep 7, 2026Updated last week
- Common SystemVerilog components☆794Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Rocket Chip Generator☆3,869Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆328Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,261Sep 8, 2026Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆568Nov 26, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,237Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,201Updated this week
- Random instruction generator for RISC-V processor verification☆1,354Sep 4, 2026Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆161Oct 31, 2024Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SERV - The SErial RISC-V CPU☆1,884Aug 25, 2026Updated 3 weeks ago
- educational microarchitectures for risc-v isa☆754Sep 1, 2025Updated last year
- CORE-V Family of RISC-V Cores☆371Mar 31, 2026Updated 5 months ago
- 32-bit Superscalar RISC-V CPU☆1,308Sep 18, 2021Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,610Sep 4, 2026Updated last week
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago
- VeeR EH2 core☆279Updated this week
- VeeR EL2 Core☆343Updated this week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆548Aug 19, 2026Updated 3 weeks ago
- A directory of Western Digital’s RISC-V SweRV Cores☆883Mar 26, 2020Updated 6 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆681Sep 8, 2026Updated last week
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,389Updated this week
- RISC-V CPU Core (RV32IM)☆1,789Sep 18, 2021Updated 4 years ago