4 stage, in-order, secure RISC-V core based on the CV32E40P
☆163Oct 31, 2024Updated last year
Alternatives and similar repositories for cv32e40s
Users that are interested in cv32e40s are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆287Nov 6, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆95Apr 1, 2026Updated 6 months ago
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated 2 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆214Oct 19, 2026Updated last week
- The multi-core cluster of a PULP system.☆122Oct 5, 2026Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆332Sep 15, 2026Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆232Jan 11, 2026Updated 9 months ago
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 3 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆733Oct 19, 2026Updated last week
- CORE-V Family of RISC-V Cores☆380Mar 31, 2026Updated 6 months ago
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 4 months ago
- VeeR EL2 Core☆349Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆647Sep 14, 2026Updated last month
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆329Oct 22, 2026Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Oct 20, 2026Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- VeeR EH2 core☆283Oct 6, 2026Updated 3 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆322Oct 17, 2023Updated 3 years ago
- RISC-V microcontroller IP for embedded, FPGA and ASIC applications☆203Oct 16, 2026Updated last week
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆250Updated this week
- Common SystemVerilog components☆810Sep 18, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆839Oct 14, 2026Updated 2 weeks ago
- Simple runtime for Pulp platforms☆56Jul 7, 2026Updated 3 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated last month
- RISC-V System on Chip Template☆162Aug 26, 2026Updated 2 months ago
- ☆144Feb 29, 2024Updated 2 years ago
- RISC-V CPU Core☆454Jun 24, 2025Updated last year
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆72Oct 9, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆384Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,135Updated this week
- Working draft of the proposed RISC-V Bitmanipulation extension☆221Mar 20, 2024Updated 2 years ago
- VeeR EH1 core☆970Jul 16, 2026Updated 3 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆132Sep 7, 2026Updated last month
- ☆16Oct 5, 2026Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,325Sep 18, 2021Updated 5 years ago