4 stage, in-order, secure RISC-V core based on the CV32E40P
☆162Oct 31, 2024Updated last year
Alternatives and similar repositories for cv32e40s
Users that are interested in cv32e40s are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆279Nov 6, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- CV32E40X Design-Verification environment☆19Jun 2, 2026Updated 3 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆212Sep 2, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆95Apr 1, 2026Updated 5 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆722Updated this week
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆316Oct 17, 2023Updated 2 years ago
- CORE-V Family of RISC-V Cores☆371Mar 31, 2026Updated 5 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 8 months ago
- The multi-core cluster of a PULP system.☆116Aug 4, 2026Updated last month
- VeeR EL2 Core☆344Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V Debug Support for our PULP RISC-V Cores☆328Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,291Aug 26, 2026Updated 3 weeks ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- ☆145Feb 29, 2024Updated 2 years ago
- RISC-V microcontroller for embedded, FPGA and ASIC applications☆202Sep 11, 2026Updated last week
- RISC-V System on Chip Template☆162Aug 26, 2026Updated 3 weeks ago
- VeeR EH2 core☆279Updated this week
- Common SystemVerilog components☆799Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆328Updated this week
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆220Mar 20, 2024Updated 2 years ago
- VeeR EH1 core☆967Jul 16, 2026Updated 2 months ago
- Simple runtime for Pulp platforms☆55Jul 7, 2026Updated 2 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,062Updated this week
- SERV - The SErial RISC-V CPU☆1,886Aug 25, 2026Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆101Aug 20, 2026Updated 3 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- GEMM and GEMM-Ops accelerator for PULP systems☆120Updated this week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆70Sep 2, 2026Updated 2 weeks ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 5 months ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆300Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- UNSUPPORTED INTERNAL toolchain builds☆49Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆240Updated this week