chili-chips-ba / openPCIELinks
Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.
☆48Updated last week
Alternatives and similar repositories for openPCIE
Users that are interested in openPCIE are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 9 months ago
- A compact, configurable RISC-V core☆12Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆51Updated 3 weeks ago
- ☆27Updated this week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- SpiceBind – spice inside HDL simulator☆56Updated 5 months ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆81Updated 2 months ago
- ☆34Updated 4 years ago
- ☆38Updated 2 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated 2 weeks ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Updated 4 months ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆25Updated 5 months ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆73Updated this week
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆95Updated last week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆77Updated last week
- IEEE P1735 decryptor for VHDL☆38Updated 10 years ago
- ☆26Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆38Updated 9 months ago
- ☆33Updated 3 years ago