chili-chips-ba / openPCIELinks
Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the Host side! Our project roots for Root Complex in 4 ways: 1) openRTL; 2) openBFM with unique sim setup, better performing than vendor TB; 3) openSoftware stack; 4) one-of-the kind openBackplane
☆13Updated this week
Alternatives and similar repositories for openPCIE
Users that are interested in openPCIE are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last month
- ☆23Updated 3 months ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- UART models for cocotb☆29Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- Library of reusable VHDL components☆28Updated last year
- SpiceBind – spice inside HDL simulator☆19Updated 2 weeks ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆23Updated this week
- Wishbone interconnect utilities☆41Updated 5 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated last month
- ☆34Updated 4 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆62Updated this week
- A compact, configurable RISC-V core☆11Updated 3 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 3 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago