RIOSLaboratory / OpenXRAM
sram/rram/mram.. compiler
☆31Updated last year
Alternatives and similar repositories for OpenXRAM:
Users that are interested in OpenXRAM are comparing it to the libraries listed below
- Open source process design kit for 28nm open process☆50Updated 10 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 weeks ago
- ☆25Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆33Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- A configurable SRAM generator☆44Updated 2 months ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- Project repo for the POSH on-chip network generator☆44Updated last year
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆31Updated 5 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆23Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆47Updated last month
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆25Updated last year
- ☆22Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- SRAM☆21Updated 4 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago