Alternatives and similar repositories for OpenXRAM

Users that are interested in OpenXRAM are comparing it to the libraries listed below

• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆72Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆58Updated 5 months ago
• lnis-uofu / FreePDK45-RRAM-Addon
  A RRAM addon for the NCSU FreePDK 45nm
  ☆25Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 3 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆166Updated last month
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆52Updated 5 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆82Updated 4 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆65Updated last week
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆79Updated 2 months ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 10 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆56Updated 3 years ago
• The-OpenROAD-Project / asap5
  ☆38Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆98Updated 2 months ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 5 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆32Updated 10 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆33Updated 4 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• aolofsson / POSH
  ☆44Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆76Updated 6 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆35Updated 8 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago