Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
☆38Jan 18, 2022Updated 4 years ago
Alternatives and similar repositories for PDK_ONC5
Users that are interested in PDK_ONC5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SMT-based-STDCELL-Layout-Generator☆20Sep 30, 2021Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆60Dec 19, 2022Updated 3 years ago
- A verilog parser☆19Apr 12, 2024Updated 2 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Mirror of Synopsys's Liberty parser library☆25Jul 6, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- ☆59Apr 8, 2024Updated 2 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆20Jul 22, 2020Updated 6 years ago
- ☆230Aug 30, 2021Updated 5 years ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Jan 7, 2026Updated 7 months ago
- PVconverter is a language translation tool which can convert the commonly used physical verification programming languages to each other.…☆21Sep 23, 2021Updated 4 years ago
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- LAYout with Gridded Objects☆35Jun 18, 2020Updated 6 years ago
- Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.☆11Aug 13, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- ☆33Jan 24, 2020Updated 6 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- Cobra-W -> Cobra-RE 将进一步 提升漏洞发现的准确性并降低漏报率（弃坑了）☆16Aug 15, 2020Updated 6 years ago
- Black Duck Detect plugin for Jenkins☆12Aug 27, 2026Updated last week
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- OpenROAD's Chatbot Assistant☆46Aug 5, 2026Updated 3 weeks ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Oct 27, 2015Updated 10 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- Jupyter kernel for Cadence SKILL☆22Feb 16, 2017Updated 9 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- EDA physical synthesis optimization kit☆69Nov 13, 2023Updated 2 years ago
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- AMC: Asynchronous Memory Compiler☆56Jun 29, 2020Updated 6 years ago
- The development tree for OpenOCD for MIPS Atlas ARC® processors☆16May 25, 2026Updated 3 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆69Dec 13, 2016Updated 9 years ago
- Inserting elements into this map yields a persistent, type-safe Index to that new element.☆13Oct 15, 2018Updated 7 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- DATC Robust Design Flow.☆36Jan 21, 2020Updated 6 years ago
- Implementation of the paper Unsupervised Domain Adaptation by Backpropagation☆11Dec 1, 2018Updated 7 years ago