Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
☆38Jan 18, 2022Updated 4 years ago
Alternatives and similar repositories for PDK_ONC5
Users that are interested in PDK_ONC5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SMT-based-STDCELL-Layout-Generator☆20Sep 30, 2021Updated 5 years ago
- Mirror of Synopsys's Liberty parser library☆24Jul 6, 2018Updated 8 years ago
- An open source PDK using TIGFET 10nm devices.☆61Dec 19, 2022Updated 3 years ago
- A verilog parser☆19Apr 12, 2024Updated 2 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Collection of macros to help with chip design in KLayout☆11Apr 13, 2017Updated 9 years ago
- Fork from https://sourceforge.net/projects/gds3d☆70Jun 11, 2024Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- Verilog-HDL codes, Tcl files, and etc. for TSMC_65nm☆12Jul 2, 2019Updated 7 years ago
- ☆62Apr 8, 2024Updated 2 years ago
- DATC RDF☆49Jul 31, 2020Updated 6 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- ☆238Aug 30, 2021Updated 5 years ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Jan 7, 2026Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Aug 20, 2017Updated 9 years ago
- ☆13Oct 23, 2022Updated 4 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆20Jul 22, 2020Updated 6 years ago
- Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.☆11Aug 13, 2021Updated 5 years ago
- Tools for FPGA Assurance Flows☆14Sep 25, 2026Updated last month
- ☆10Nov 2, 2023Updated 3 years ago
- ☆22Oct 26, 2025Updated last year
- LAYout with Gridded Objects☆36Jun 18, 2020Updated 6 years ago
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 7 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率（弃坑了）☆16Aug 15, 2020Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Copyleftist's Standard Cell Library☆107May 2, 2024Updated 2 years ago
- PVconverter is a language translation tool which can convert the commonly used physical verification programming languages to each other.…☆21Sep 23, 2021Updated 5 years ago
- ☆33Jan 24, 2020Updated 6 years ago
- Source of the Free PDK documentation website.☆23Updated this week
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- ☆10Oct 14, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Jupyter kernel for Cadence SKILL☆22Feb 16, 2017Updated 9 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 9 years ago
- The development tree for OpenOCD for MIPS Atlas ARC® processors☆16Sep 14, 2026Updated last month
- Inserting elements into this map yields a persistent, type-safe Index to that new element.☆13Oct 15, 2018Updated 8 years ago
- OpenROAD's Chatbot Assistant☆48Updated this week
- EE 260 Winter 2017: Advanced VLSI Design☆69Dec 13, 2016Updated 9 years ago
- ☆10Feb 26, 2026Updated 8 months ago