NeuroFan / Algorithmic-SAR-ADC-simulation-files
HSPICE and MATLAB simulation files of a tracking SAR ADC
☆23Updated 7 months ago
Alternatives and similar repositories for Algorithmic-SAR-ADC-simulation-files:
Users that are interested in Algorithmic-SAR-ADC-simulation-files are comparing it to the libraries listed below
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆51Updated 6 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆10Updated 5 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆30Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆24Updated 5 years ago
- Python library for SerDes modelling☆63Updated 6 months ago
- A 10bit SAR ADC in Sky130☆22Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆42Updated 4 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆40Updated 8 years ago
- Model SAR ADC with python!☆19Updated 2 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆25Updated 3 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆26Updated 3 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆62Updated last year
- All digital PLL☆27Updated 7 years ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆23Updated 6 years ago
- FIR implemention with Verilog☆45Updated 5 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆28Updated 7 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆21Updated 5 years ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆69Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆43Updated 3 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆29Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆39Updated 11 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆48Updated last year
- ☆19Updated last year
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆18Updated 5 months ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆9Updated 3 years ago