NeuroFan / Algorithmic-SAR-ADC-simulation-filesLinks
HSPICE and MATLAB simulation files of a tracking SAR ADC
☆26Updated last year
Alternatives and similar repositories for Algorithmic-SAR-ADC-simulation-files
Users that are interested in Algorithmic-SAR-ADC-simulation-files are comparing it to the libraries listed below
Sorting:
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆67Updated 7 years ago
- Python library for SerDes modelling☆74Updated last year
- A 10bit SAR ADC in Sky130☆25Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆37Updated 3 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆79Updated 2 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆186Updated last year
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆35Updated 6 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆81Updated 3 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆170Updated 2 months ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆232Updated 3 months ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆52Updated 8 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Updated 3 years ago
- Verilog RTL Design☆46Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆31Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆71Updated last month
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆95Updated last year
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆36Updated 2 years ago
- Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation☆12Updated 5 years ago
- Model SAR ADC with python!☆22Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆20Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year