tiemingsun / Noise-Shaping-SAR-ADC
Simulink model for noise shaping SAR ADC
☆9Updated 5 years ago
Alternatives and similar repositories for Noise-Shaping-SAR-ADC:
Users that are interested in Noise-Shaping-SAR-ADC are comparing it to the libraries listed below
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆33Updated last year
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆18Updated last year
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆19Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆22Updated 6 years ago
- All digital PLL☆28Updated 7 years ago
- A 10bit SAR ADC in Sky130☆22Updated 2 years ago
- A collection of license features from a varity of EDA vendors☆50Updated last year
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆27Updated 3 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆66Updated last year
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆46Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- Python library for SerDes modelling☆66Updated 8 months ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆11Updated 5 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆30Updated 3 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- Digital Standard Cells based SAR ADC☆13Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆55Updated 6 years ago
- Must-have verilog systemverilog modules☆31Updated 2 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆23Updated 4 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆25Updated 5 years ago
- Audio filtering with pyfda and cocotb☆10Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago
- This is a demo for still image compression application☆13Updated 6 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆17Updated 5 years ago
- Completed LDO Design for Skywaters 130nm☆14Updated 2 years ago