Alternatives and similar repositories for 8bit_sar_adc:

Users that are interested in 8bit_sar_adc are comparing it to the libraries listed below

• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆48Updated 10 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆30Updated 4 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆67Updated 2 years ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆30Updated 2 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆32Updated 9 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆19Updated 4 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆22Updated 2 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆58Updated 6 months ago
• filipamator / adpll
  All digital PLL
  ☆27Updated 7 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 3 years ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆26Updated 3 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆19Updated 4 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆50Updated 4 years ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆29Updated 5 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆43Updated last year
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆62Updated last year
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆30Updated 4 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆15Updated 5 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆145Updated 3 months ago
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆30Updated 6 years ago
• freecores / apbi2c
  APB to I2C
  ☆39Updated 10 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆61Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆30Updated 2 years ago
• A-suozhang / Verilog_Uart_With_Fifo
  Implemented The UART with FIFO
  ☆12Updated 5 years ago