C-Aniruddh / 8bit_sar_adc
Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
☆24Updated 6 years ago
Alternatives and similar repositories for 8bit_sar_adc
Users that are interested in 8bit_sar_adc are comparing it to the libraries listed below
Sorting:
- Delta-sigma ADC,PDM audio FPGA Implementation☆70Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆31Updated 3 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆28Updated 3 years ago
- All digital PLL☆28Updated 7 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆27Updated 6 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆11Updated 5 years ago
- Reed Solomon Encoder and Decoder Digital IP☆20Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆23Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆68Updated last year
- A 10bit SAR ADC in Sky130☆23Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 9 months ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Updated 6 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21Updated last year
- FFT implementation using CORDIC algorithm written in Verilog.☆32Updated 6 years ago
- ☆41Updated 3 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆49Updated 3 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆16Updated 2 weeks ago
- Single Port RAM, Dual Port RAM, FIFO☆24Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- ☆12Updated 10 months ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆23Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆59Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆45Updated 3 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆19Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year