C-Aniruddh / 8bit_sar_adcLinks
Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
☆26Updated 7 years ago
Alternatives and similar repositories for 8bit_sar_adc
Users that are interested in 8bit_sar_adc are comparing it to the libraries listed below
Sorting:
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆175Updated 10 months ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆34Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆63Updated 4 years ago
- configurable cordic core in verilog☆52Updated 11 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- All digital PLL☆28Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆67Updated 3 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆54Updated 2 years ago
- I2C Master and Slave☆37Updated 10 years ago
- Verilog modules required to get the OV7670 camera working☆73Updated 7 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆71Updated last year
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- FPGA Technology Exchange Group相关文件管理☆51Updated 2 weeks ago
- A simple implementation of a UART modem in Verilog.☆155Updated 3 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆109Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Gigabit Ethernet UDP communication driver☆79Updated 6 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆13Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆67Updated 4 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago