Alternatives and similar repositories for 8bit_sar_adc

Users that are interested in 8bit_sar_adc are comparing it to the libraries listed below

• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆41Updated 3 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆168Updated 9 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆52Updated 11 years ago
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆32Updated 6 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆148Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆32Updated 3 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 6 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆64Updated last year
• muhammadaldacher / RF-design-of-2.4-GHz-LNA
  This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
  ☆14Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆62Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆59Updated 4 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆47Updated last week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …
  ☆31Updated 6 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆70Updated 3 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆57Updated 9 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆53Updated 2 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆64Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆178Updated 12 years ago
• antmicro / nvme-verilog-pcie
  ☆73Updated 3 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆72Updated 7 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• ericgineer / CORDIC
  The CORDIC algorithm implemented in Octave/MATLAB and Verilog
  ☆31Updated 10 years ago