Alternatives and similar repositories for 8bit_sar_adc

Users that are interested in 8bit_sar_adc are comparing it to the libraries listed below

• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆37Updated 3 years ago
• muhammadaldacher / RF-design-of-2.4-GHz-LNA
  This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
  ☆12Updated 6 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆186Updated last year
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆115Updated last year
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆53Updated 11 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆72Updated 8 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆74Updated 5 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆72Updated last month
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆81Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆35Updated 6 months ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆33Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆47Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆34Updated 5 years ago
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆80Updated 2 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …
  ☆36Updated 6 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆76Updated 7 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆67Updated 4 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆168Updated 4 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆60Updated 3 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆54Updated last month