shalan / AD_SAR_ADCLinks
Digital Standard Cells based SAR ADC
☆14Updated 4 years ago
Alternatives and similar repositories for AD_SAR_ADC
Users that are interested in AD_SAR_ADC are comparing it to the libraries listed below
Sorting:
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- Open Source PHY v2☆30Updated last year
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆24Updated 6 years ago
- SRAM☆23Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 3 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- ☆44Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year
- ☆17Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Hardware Formal Verification☆15Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆28Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 6 months ago
- Open source process design kit for 28nm open process☆61Updated last year
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 months ago
- Automatic generation of real number models from analog circuits☆43Updated last year
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 8 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆49Updated 4 years ago
- ☆20Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago