shalan / AD_SAR_ADCLinks
Digital Standard Cells based SAR ADC
☆14Updated 4 years ago
Alternatives and similar repositories for AD_SAR_ADC
Users that are interested in AD_SAR_ADC are comparing it to the libraries listed below
Sorting:
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆26Updated 6 years ago
- SRAM☆22Updated 5 years ago
- Open Source PHY v2☆31Updated last year
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- ☆44Updated 5 years ago
- This is a tutorial on standard digital design flow☆81Updated 4 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Intel's Analog Detailed Router☆39Updated 6 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆14Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 4 years ago
- Automatic generation of real number models from analog circuits☆47Updated last year
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 7 months ago
- Open source process design kit for 28nm open process☆72Updated last year
- ☆14Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- ☆17Updated 3 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆23Updated 2 years ago
- ☆20Updated last year
- ☆20Updated 4 years ago
- CMake based hardware build system☆35Updated 3 weeks ago
- A configurable SRAM generator☆56Updated 4 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆37Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago