ADC-TEAM2020 / avsdadc_3v3
This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.
☆19Updated 4 years ago
Alternatives and similar repositories for avsdadc_3v3:
Users that are interested in avsdadc_3v3 are comparing it to the libraries listed below
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆23Updated 6 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆18Updated last year
- A 10bit SAR ADC in Sky130☆22Updated 2 years ago
- ☆12Updated 2 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆15Updated 5 years ago
- ☆40Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆33Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆30Updated 3 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- ☆16Updated 2 years ago
- repository for a bandgap voltage reference in SKY130 technology☆37Updated 2 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆23Updated 4 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆16Updated 10 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- A tiny Python package to parse spice raw data files.☆49Updated 2 years ago
- Skywaters 130nm Klayout PDK☆23Updated 2 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆18Updated 4 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated 9 months ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago