ADC-TEAM2020 / avsdadc_3v3
This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.
☆18Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for avsdadc_3v3
- ☆16Updated 2 years ago
- A 10bit SAR ADC in Sky130☆20Updated last year
- ☆12Updated 2 years ago
- ☆39Updated 2 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆20Updated 5 years ago
- repository for a bandgap voltage reference in SKY130 technology☆34Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆21Updated 5 months ago
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated 11 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆28Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆28Updated last year
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆13Updated 4 years ago
- Completed LDO Design for Skywaters 130nm☆14Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆35Updated 2 weeks ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆19Updated 2 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆56Updated this week
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆13Updated 5 years ago
- MOSIS MPW Test Data and SPICE Models Collections☆26Updated 4 years ago
- cdsAsync: An Asynchronous VLSI Toolset & Schematic Library☆25Updated 5 years ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆21Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- ☆20Updated 2 years ago