zlijingtao / Digital-Calibration-of-SAR-ADCLinks
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
☆62Updated 7 years ago
Alternatives and similar repositories for Digital-Calibration-of-SAR-ADC
Users that are interested in Digital-Calibration-of-SAR-ADC are comparing it to the libraries listed below
Sorting:
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆24Updated 11 months ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆28Updated 4 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆11Updated 5 years ago
- ADC Performance Survey 1997-2024 (ISSCC & VLSI Circuit Symposium)☆195Updated 9 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆28Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆67Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆165Updated 6 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆31Updated 3 years ago
- ☆60Updated 11 months ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆50Updated 3 years ago
- Python library for SerDes modelling☆69Updated 10 months ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆25Updated 6 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- A 10bit SAR ADC in Sky130☆23Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆46Updated 5 years ago
- All digital PLL☆28Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆14Updated last year
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆138Updated this week
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆30Updated 8 years ago
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- ☆70Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆10Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- ☆24Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- Some useful documents of Synopsys☆73Updated 3 years ago