zlijingtao / Digital-Calibration-of-SAR-ADCLinks
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
☆67Updated 7 years ago
Alternatives and similar repositories for Digital-Calibration-of-SAR-ADC
Users that are interested in Digital-Calibration-of-SAR-ADC are comparing it to the libraries listed below
Sorting:
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆184Updated 11 months ago
- SPI interface connect to APB BUS with Verilog HDL☆37Updated 4 years ago
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆77Updated 2 years ago
- Verilog RTL Design☆45Updated 4 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆32Updated 4 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆85Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- ☆69Updated 9 years ago
- AXI总线连接器☆105Updated 5 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆221Updated 2 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆91Updated last year
- ☆76Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆53Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆141Updated 6 years ago
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago