zlijingtao / Digital-Calibration-of-SAR-ADCLinks
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
☆67Updated 7 years ago
Alternatives and similar repositories for Digital-Calibration-of-SAR-ADC
Users that are interested in Digital-Calibration-of-SAR-ADC are comparing it to the libraries listed below
Sorting:
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Updated last year
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆33Updated 4 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆186Updated last year
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆241Updated 4 months ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆80Updated 2 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Updated 6 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆38Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆81Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆99Updated last year
- Python library for SerDes modelling☆79Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- A 10bit SAR ADC in Sky130☆26Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆54Updated 3 weeks ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Updated 6 years ago
- Pipeline FFT Implementation in Verilog HDL☆153Updated 6 years ago
- ☆74Updated last year
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆175Updated 3 months ago
- Verilog RTL Design☆46Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆73Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61Updated 2 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆29Updated 5 years ago