Alternatives and similar repositories for sar-adc

Users that are interested in sar-adc are comparing it to the libraries listed below

• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆26Updated 6 years ago
• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆25Updated 3 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆47Updated last year
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆37Updated 3 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆29Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• richard259 / serdespy
  Python library for SerDes modelling
  ☆74Updated last year
• shalan / Awesome-Sky130-IPs
  ☆14Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago
• rnunes2311 / SAR_ADC_12bit
  12 bit SAR ADC IP in Skywater 130 nm PDK
  ☆20Updated last year
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆41Updated 2 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆115Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆25Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• w32agobot / SKY130_SAR-ADC
  Fully-differential asynchronous non-binary 12-bit SAR-ADC
  ☆36Updated 2 years ago
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆20Updated 5 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆63Updated this week
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆53Updated 3 years ago
• NeuroFan / Algorithmic-SAR-ADC-simulation-files
  HSPICE and MATLAB simulation files of a tracking SAR ADC
  ☆26Updated last year
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆18Updated 2 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆67Updated 3 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆52Updated 4 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆142Updated last week
• filipamator / adpll
  All digital PLL
  ☆28Updated 8 years ago
• medwatt / gmid
  Python script for generating lookup tables for the gm/ID design methodology and much more ...
  ☆109Updated last month
• ChrisZonghaoLi / pystateye
  pystateye - A Python Implementation of Statistical Eye Analysis and Visualization
  ☆14Updated last year