w32agobot / SKY130_SAR-ADCLinks
Fully-differential asynchronous non-binary 12-bit SAR-ADC
☆36Updated 2 years ago
Alternatives and similar repositories for SKY130_SAR-ADC
Users that are interested in SKY130_SAR-ADC are comparing it to the libraries listed below
Sorting:
- A 10bit SAR ADC in Sky130☆25Updated 3 years ago
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 2 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆79Updated 2 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated 2 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆186Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆63Updated this week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆37Updated 3 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆14Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆22Updated 2 years ago
- ☆17Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆26Updated 6 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 4 years ago
- ☆83Updated 10 months ago
- This project shows the design process of the main blocks of a typical RX frontend system.☆25Updated 4 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆29Updated 3 years ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆49Updated 3 months ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆108Updated 2 weeks ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆26Updated last year
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆12Updated 6 years ago
- Circuit Automatic Characterization Engine☆51Updated 10 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆66Updated last week
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆75Updated 8 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆76Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆95Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆103Updated last year