Verilog implementation of Softmax function
☆82Jul 27, 2022Updated 4 years ago
Alternatives and similar repositories for softmax
Users that are interested in softmax are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 6 years ago
- ☆11Nov 22, 2025Updated 9 months ago
- ViTALiTy (HPCA'23) Code Repository☆25Mar 13, 2023Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆13Nov 1, 2021Updated 4 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- ☆24Jun 17, 2014Updated 12 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆17Sep 21, 2025Updated 11 months ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 3 weeks ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆575Jan 5, 2019Updated 7 years ago
- Research and Materials on Hardware implementation of Transformer Model☆311Feb 28, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- IC implementation of Systolic Array for TPU☆370Oct 21, 2024Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆267Mar 24, 2024Updated 2 years ago
- A network slimming-based pruning method for YOLOv8.☆38Jun 10, 2024Updated 2 years ago
- ☆19Sep 16, 2022Updated 3 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Simulator for BitFusion☆103Aug 6, 2020Updated 6 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆230Aug 4, 2019Updated 7 years ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 4 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆23May 6, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An open-source UCIe implementation developed at UC Berkeley.☆20Jul 8, 2024Updated 2 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆61Jul 25, 2019Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆47Jul 28, 2017Updated 9 years ago
- State of the art 84.7% accuracy on SleepEDF-78 and 88.4% SHHS Datasset☆10Apr 28, 2025Updated last year
- An out-of-order processor that supports multiple instruction sets.☆23Aug 23, 2022Updated 4 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆33Mar 7, 2024Updated 2 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 4 years ago
- 使用Cordic算法函数运算，在资源受限的设备上运行（如资源较少的FPGA、嵌入式MCU），避免了浮点运算、乘法、除法，只用移位 和加法函数的计算。☆14Mar 22, 2024Updated 2 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This repository contains codes and texts related with the FPGA RTL Implementation of the Delay and Sum Beamformer☆23Apr 4, 2022Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆176Jul 25, 2019Updated 7 years ago
- A DNN Accelerator implemented with RTL.☆71Jan 9, 2025Updated last year
- An FPGA design for simulating biological neurons☆19Jul 5, 2024Updated 2 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- FPU Generator☆20Aug 15, 2026Updated 2 weeks ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year