Verilog implementation of Softmax function
☆80Jul 27, 2022Updated 3 years ago
Alternatives and similar repositories for softmax
Users that are interested in softmax are comparing it to the libraries listed below
Sorting:
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- ViTALiTy (HPCA'23) Code Repository☆23Mar 13, 2023Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- ☆11Nov 22, 2025Updated 4 months ago
- ☆28Feb 5, 2020Updated 6 years ago
- ☆13Nov 1, 2021Updated 4 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- ☆15Sep 16, 2022Updated 3 years ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码,它能使用LLM对文本数据进行暴力的压缩,达到极高的压缩率。☆22Nov 24, 2024Updated last year
- ☆21Jun 17, 2014Updated 11 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- An open-source UCIe implementation developed at UC Berkeley.☆20Jul 8, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆234Mar 24, 2024Updated last year
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆549Jan 5, 2019Updated 7 years ago
- IC implementation of Systolic Array for TPU☆343Oct 21, 2024Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- Research and Materials on Hardware implementation of Transformer Model☆299Feb 28, 2025Updated last year
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆21May 6, 2024Updated last year
- Memory Compiler Tutorial☆13Aug 2, 2022Updated 3 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆28Apr 7, 2025Updated 11 months ago
- Small-scale Tensor Processing Unit built on an FPGA☆221Aug 4, 2019Updated 6 years ago
- A network slimming-based pruning method for YOLOv8.☆38Jun 10, 2024Updated last year
- Simulator for BitFusion☆101Aug 6, 2020Updated 5 years ago
- An out-of-order processor that supports multiple instruction sets.☆21Aug 23, 2022Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Jul 28, 2017Updated 8 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆59Jul 25, 2019Updated 6 years ago
- State of the art 84.7% accuracy on SleepEDF-78 and 88.4% SHHS Datasset☆10Apr 28, 2025Updated 10 months ago
- A DNN Accelerator implemented with RTL.☆69Jan 9, 2025Updated last year
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Mar 7, 2024Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆164May 10, 2025Updated 10 months ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- The code of SpikingSSMs: Learning Long Sequences with Sparse and Parallel Spiking State Space Models☆22Apr 16, 2025Updated 11 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆173Jul 25, 2019Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago