maomran / softmaxLinks
Verilog implementation of Softmax function
☆75Updated 3 years ago
Alternatives and similar repositories for softmax
Users that are interested in softmax are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆174Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- ☆71Updated 6 years ago
- IC implementation of TPU☆134Updated 5 years ago
- ☆120Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆138Updated 6 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆43Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆118Updated 3 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆89Updated 5 years ago
- ☆37Updated 6 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Library of approximate arithmetic circuits☆57Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆59Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 5 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆233Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆103Updated 9 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆69Updated 5 years ago
- IC implementation of Systolic Array for TPU☆296Updated last year
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated 2 weeks ago
- This repository contains full code of Softmax Layer in Verilog☆20Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆195Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week