losfair / MagiCoreLinks
An out-of-order processor that supports multiple instruction sets.
☆19Updated 2 years ago
Alternatives and similar repositories for MagiCore
Users that are interested in MagiCore are comparing it to the libraries listed below
Sorting:
- SpinalHDL - Cryptography libraries☆56Updated last year
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Dual-issue RV64IM processor for fun & learning☆62Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆70Updated this week
- chipyard in mill :P☆78Updated last year
- Chisel Cheatsheet☆33Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Simple runtime for Pulp platforms☆48Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- Open source high performance IEEE-754 floating unit☆80Updated last year
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Open-source non-blocking L2 cache☆44Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- Useful utilities for BAR projects☆32Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆93Updated 2 years ago
- Open-source high-performance non-blocking cache☆86Updated last month
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 3 months ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Updated 3 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆22Updated 4 years ago