Alternatives and similar repositories for MagiCore

Users that are interested in MagiCore are comparing it to the libraries listed below

• SpinalHDL / SpinalCrypto
  SpinalHDL - Cryptography libraries
  ☆58Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated 2 months ago
• ucb-bar / testchipip
  ☆87Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆92Updated 3 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆106Updated last month
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆155Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• nbdd0121 / muntjac-soc
  SoC for muntjac
  ☆12Updated 6 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• datenlord / poseidon-spinal
  The hardware implementation of Poseidon hash function in SpinalHDL
  ☆20Updated 3 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆31Updated 4 years ago
• sequencer / arithmetic
  ☆33Updated 9 months ago
• asinghani / crypto-accelerator-chip
  Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…
  ☆23Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆169Updated 5 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• pulp-platform / redmule
  ☆90Updated 3 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆37Updated last month
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• huxuan0307 / XuanTieC910
  Rewrite XuanTieC910 with chisel3
  ☆12Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆27Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆52Updated this week