losfair/MagiCore external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

losfair/MagiCore

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/losfair/MagiCore)

Close

losfair / MagiCoreView on GitHubMore

• External links
• Readme badge

An out-of-order processor that supports multiple instruction sets.

☆21Aug 23, 2022Updated 3 years ago

Alternatives and similar repositories for MagiCore

Users that are interested in MagiCore are comparing it to the libraries listed below

• losfair / Violet

  View on GitHub
  Superscalar RISC-V processor written in Clash.
  ☆35Aug 23, 2022Updated 3 years ago
• adamgallas / SpinalDLA

  View on GitHub
  [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…
  ☆21May 6, 2024Updated last year
• dhanna11 / OpenGPU

  View on GitHub
  ☆11Feb 16, 2019Updated 7 years ago
• NOP-Processor / NOP-SoC

  View on GitHub
  System-on-chip design for NOP in NSCSCC 2023.
  ☆12Aug 21, 2023Updated 2 years ago
• HamoElder / MAGI_PROJECT

  View on GitHub
  ☆10Jan 25, 2023Updated 3 years ago
• ZLXT / SpinalHDL-MIPS

  View on GitHub
  Translate the source code of Veriog version to Spinalhdl version
  ☆10Jul 1, 2021Updated 4 years ago
• datenlord / poseidon-spinal

  View on GitHub
  The hardware implementation of Poseidon hash function in SpinalHDL
  ☆21Jun 5, 2022Updated 3 years ago
• lycfly / EasyNPU

  View on GitHub
  A small Neural Network Processor for Edge devices.
  ☆18Nov 22, 2022Updated 3 years ago
• HEAP-Lab-VT / ASIC-DEFLATE-for-memory

  View on GitHub
  hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel
  ☆16Nov 15, 2024Updated last year
• voldemoriarty / Matmul

  View on GitHub
  Matrix Multiplication in Hardware
  ☆16Jun 3, 2020Updated 5 years ago
• isnthzy / lightsss-chiplab

  View on GitHub
  本项目已被合并至官方Chiplab中
  ☆13Jan 13, 2025Updated last year
• proteus-core / proteus

  View on GitHub
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆61Jan 7, 2026Updated 2 months ago
• c-thaler / DmaUnit

  View on GitHub
  A simple AXI4 DMA unit written in SpinalHDL.
  ☆18Apr 18, 2020Updated 5 years ago
• MrAMS / verilogModuleAddPrefix

  View on GitHub
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Mar 4, 2024Updated 2 years ago
• tomverbeure / usb_system

  View on GitHub
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Jan 9, 2022Updated 4 years ago
• antmicro / fastvdma

  View on GitHub
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Mar 6, 2026Updated 2 weeks ago
• IBM / esp-chisel-accelerators

  View on GitHub
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Feb 1, 2020Updated 6 years ago
• SpinalHDL / rvls

  View on GitHub
  RISCV lock-step checker based on Spike
  ☆14Mar 6, 2026Updated 2 weeks ago
• sequencer / arithmetic

  View on GitHub
  ☆33Mar 20, 2025Updated last year
• yportne13 / SpinalResNet

  View on GitHub
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆35Mar 14, 2021Updated 5 years ago
• fluctlight001 / SampleCPU

  View on GitHub
  ☆13Oct 26, 2022Updated 3 years ago
• jiegec / fpu-wrappers

  View on GitHub
  Wrappers for open source FPU hardware implementations.
  ☆37Nov 27, 2025Updated 3 months ago
• ucb-bar / block-inclusivecache-sifive

  View on GitHub
  ☆12Jan 19, 2022Updated 4 years ago
• BakrN / vortex

  View on GitHub
  ☆17Mar 8, 2025Updated last year
• bijiye / Xray-script

  View on GitHub
  Xray一键安装脚本，支持节点自动生成伪装站，支持和宝塔面板共存
  ☆13Jan 17, 2023Updated 3 years ago
• theSergeyGusev / simple10GbaseR

  View on GitHub
  FPGA Low latency 10GBASE-R PCS
  ☆12May 23, 2023Updated 2 years ago
• FPSG-UIUC / micro24-fusemax-artifact

  View on GitHub
  MICRO 2024 Evaluation Artifact for FuseMax
  ☆16Aug 26, 2024Updated last year
• Gianthard-cyh / riscv-pte

  View on GitHub
  RISC-V Sv39 Page Table Entry Visualization Tool
  ☆18May 20, 2025Updated 10 months ago
• freechipsproject / chisel-coverage

  View on GitHub
  A coverage library for Chisel designs
  ☆11Mar 12, 2020Updated 6 years ago
• antmicro / usb-test-suite-cocotb-usb

  View on GitHub
  ☆10Apr 8, 2021Updated 4 years ago
• rgb000000 / eyeriss-chisel3

  View on GitHub
  eyeriss-chisel3
  ☆41May 2, 2022Updated 3 years ago
• KULeuven-MICAS / zigzag-llm

  View on GitHub
  Model LLM inference on single-core dataflow accelerators
  ☆18Dec 16, 2025Updated 3 months ago
• sweriko / westwelt-v0

  View on GitHub
  my first ever browser game
  ☆10Jun 21, 2025Updated 9 months ago
• riscvarchive / riscv-zfinx

  View on GitHub
  ☆12Feb 15, 2024Updated 2 years ago
• Chlorophytus / broccoli

  View on GitHub
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11May 3, 2023Updated 2 years ago
• hjking / mydotfiles

  View on GitHub
  my rc files
  ☆12Mar 16, 2016Updated 10 years ago
• blackmesalabs / eda_ai_assist

  View on GitHub
  AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.
  ☆28Updated this week
• stackos / soft-gles2

  View on GitHub
  OpenGL ES 2.0 soft rendering pipeline implemented in C++.
  ☆11Aug 15, 2019Updated 6 years ago
• bespoke-silicon-group / bsg_sv2v

  View on GitHub
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Apr 13, 2023Updated 2 years ago