An out-of-order processor that supports multiple instruction sets.
☆23Aug 23, 2022Updated 3 years ago
Alternatives and similar repositories for MagiCore
Users that are interested in MagiCore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 3 years ago
- SQLite-based on-disk cache for Rust.☆25Jul 29, 2024Updated last year
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆22May 6, 2024Updated 2 years ago
- Blackwire SpinalHDL components implementing WireGuard primitives☆16Aug 16, 2023Updated 2 years ago
- Translate the source code of Veriog version to Spinalhdl version☆10Jul 1, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆10Jan 25, 2023Updated 3 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 6 months ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 6 years ago
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- 本项目已被合并至官方Chiplab中☆14Jan 13, 2025Updated last year
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆62Jun 18, 2026Updated last month
- verilog module add prefix script 可用于ysyx项目添加学号☆13Mar 4, 2024Updated 2 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 4 months ago
- 本仓库用于开源分享本人的第九届龙芯杯个人赛参赛作品☆15Aug 27, 2025Updated 10 months ago
- ☆37Mar 20, 2025Updated last year
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 7 months ago
- A classic five stage pipelined processor☆13Mar 13, 2024Updated 2 years ago
- ☆13Oct 26, 2022Updated 3 years ago
- RISCV lock-step checker based on Spike☆15Mar 6, 2026Updated 4 months ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Xray一键安装脚本，支持节点自动生成伪装站，支持和宝塔面板共存☆14Jan 17, 2023Updated 3 years ago
- RISC-V Sv39 Page Table Entry Visualization Tool☆18May 20, 2025Updated last year
- ☆12Jan 19, 2022Updated 4 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- my first ever browser game☆10Jun 21, 2025Updated last year
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 5 months ago
- my rc files☆12Mar 16, 2016Updated 10 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- OpenGL ES 2.0 soft rendering pipeline implemented in C++.☆11Aug 15, 2019Updated 6 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆17Aug 26, 2024Updated last year
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago