☆28Feb 5, 2020Updated 6 years ago
Alternatives and similar repositories for MNIST_Classification_FPGA
Users that are interested in MNIST_Classification_FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Nov 22, 2022Updated 3 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆18Oct 11, 2019Updated 6 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 9 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆35Dec 26, 2023Updated 2 years ago
- State of the art 84.7% accuracy on SleepEDF-78 and 88.4% SHHS Datasset☆10Apr 28, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆17May 5, 2020Updated 6 years ago
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆26Mar 21, 2018Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 10 years ago
- Verilog implementation of Softmax function☆82Jul 27, 2022Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆34Jun 27, 2024Updated 2 years ago
- "智能公交系统电子站牌设计"毕业设计单片机和微信小程序代码☆14Jan 11, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- ☆35Sep 17, 2021Updated 4 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- C++ code for HLS FPGA implementation of transformer☆24Sep 11, 2024Updated last year
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆30Mar 18, 2023Updated 3 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Signal generator designed with Nexy4 FPGA☆13May 14, 2023Updated 3 years ago
- RISC-V RV32E core designed for minimal area☆27Nov 17, 2024Updated last year
- Open hardware & software DIY spin coater☆21Dec 2, 2025Updated 6 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A Mel-frequency cepstrum core in FPGA☆21Jun 30, 2021Updated 5 years ago
- Autonomous drone using detected ball to command the direction of the drone☆26Nov 1, 2018Updated 7 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog 。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Mar 10, 2019Updated 7 years ago
- 七路图像在FPGA中实现拼接，代码会不断添加进来。☆29Aug 17, 2021Updated 4 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- CDF 5/3 & CDF 9/7 Discrete Wavelet Transform☆17Oct 6, 2015Updated 10 years ago
- A novel BCI-based messaging web application that uses P300 speller and emotion detection to bridge the gap in social media accessibility …☆12Aug 31, 2021Updated 4 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 使用肤色颜色空间建模+连通域处理及分析和Harr-cascade 方法进行人脸检测。1建立多种肤色模型，结合数学形态学滤波，完成人脸检测； 2利用Matlab 自带的计算机视觉系统工具箱实现单人及多人的人脸检测。☆13Nov 23, 2018Updated 7 years ago
- A collection of my FPGA projects and experiments.☆13May 3, 2022Updated 4 years ago
- Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK☆16Dec 2, 2018Updated 7 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆40Feb 18, 2024Updated 2 years ago
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- 🎙️ CosyVoice All-in-One Docker - Production-ready TTS with Web UI, REST API & Voice Cloning☆73Jan 18, 2026Updated 5 months ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆38Jun 7, 2022Updated 4 years ago