grant4001 / MNIST_Classification_FPGALinks
☆26Updated 5 years ago
Alternatives and similar repositories for MNIST_Classification_FPGA
Users that are interested in MNIST_Classification_FPGA are comparing it to the libraries listed below
Sorting:
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- ☆34Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆23Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- IC implementation of TPU☆130Updated 5 years ago
- ☆65Updated 6 years ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆33Updated 10 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆52Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆160Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- ☆60Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 3 weeks ago