risclite / verilog-dividerLinks
a super-simple pipelined verilog divider. flexible to define stages
☆57Updated 6 years ago
Alternatives and similar repositories for verilog-divider
Users that are interested in verilog-divider are comparing it to the libraries listed below
Sorting:
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Basic RISC-V Test SoC☆140Updated 6 years ago
- Verilog digital signal processing components☆151Updated 2 years ago
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆153Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆170Updated this week
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AHB3-Lite Interconnect☆90Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆139Updated last year
- ☆68Updated 9 years ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- Verilog UART☆178Updated 12 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- Mathematical Functions in Verilog☆94Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- I2C controller core☆47Updated 2 years ago
- round robin arbiter☆75Updated 11 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆110Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆88Updated 2 years ago