risclite / verilog-divider
a super-simple pipelined verilog divider. flexible to define stages
☆55Updated 5 years ago
Alternatives and similar repositories for verilog-divider
Users that are interested in verilog-divider are comparing it to the libraries listed below
Sorting:
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆100Updated 3 years ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Verilog digital signal processing components☆134Updated 2 years ago
- An implementation of the CORDIC algorithm in Verilog.☆93Updated 6 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆147Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆146Updated 2 months ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆120Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆70Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- ☆62Updated 9 years ago
- Pipeline FFT Implementation in Verilog HDL☆112Updated 6 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- Altera Advanced Synthesis Cookbook 11.0☆103Updated 2 years ago
- Simple single-port AXI memory interface☆41Updated 11 months ago