WangXuan95 / LLMALinks
LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码,它能使用LLM对文本数据进行暴力的压缩,达到极高的压缩率。
☆17Updated 7 months ago
Alternatives and similar repositories for LLMA
Users that are interested in LLMA are comparing it to the libraries listed below
Sorting:
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆24Updated last year
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆19Updated 6 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 6 months ago
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated this week
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆18Updated 3 months ago
- ☆47Updated 2 months ago
- gem5 FS模式实验手册☆43Updated 2 years ago
- ☆31Updated 3 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 6 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 9 months ago
- 给NEMU移植Linux Kernel!☆18Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆17Updated 3 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆35Updated last month
- ☆24Updated 3 months ago
- ☆22Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆32Updated last year
- An almost empty chisel project as a starting point for hardware design☆32Updated 5 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last month
- Xiangshan deterministic workloads generator☆19Updated last month
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- ☆20Updated last month
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆19Updated 8 months ago