WangXuan95 / LLMA
LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。
☆17Updated 5 months ago
Alternatives and similar repositories for LLMA
Users that are interested in LLMA are comparing it to the libraries listed below
Sorting:
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆23Updated last year
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 7 months ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆13Updated 4 months ago
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 3 years ago
- ☆22Updated 2 years ago
- ☆20Updated last month
- This is an IDE for YSYX_NPC debuging☆12Updated 5 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last month
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆17Updated 4 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated 2 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated this week
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 4 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated this week
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated last month
- 给NEMU移植Linux Kernel!☆17Updated last month
- An almost empty chisel project as a starting point for hardware design☆31Updated 3 months ago
- ☆42Updated 3 weeks ago
- ☆14Updated last month
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- A Toy-Purpose TPU Simulator☆18Updated 11 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆30Updated last month
- Vitis 部署加速器工作流介绍☆10Updated 4 months ago
- ☆11Updated 3 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆39Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago