Top-level repository of ACT Ecosystem
☆28Jun 8, 2026Updated 2 months ago
Alternatives and similar repositories for act
Users that are interested in act are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 3 months ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆23Oct 31, 2024Updated last year
- SmoothE: Differentiable E-Graph Extraction (ASPLOS'25 Best Paper)☆34Jan 15, 2026Updated 6 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆18Feb 25, 2026Updated 5 months ago
- Virtual Decoupled Cores: Composable Programming Framework and Runtime for Async GPUs☆20Updated this week
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated last month
- MLIR-in as a compiler stack for ucb-bar☆18Updated this week
- Verified graph rewriting (for dataflow circuits).☆27Jul 15, 2026Updated 3 weeks ago
- ☆30Updated this week
- Exact Symbolic Reasoning via Boolean Equality Saturation☆25Jan 7, 2026Updated 7 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- MLIR+EqSat☆30Jan 10, 2026Updated 6 months ago
- TensorRight: Automated Verification of Tensor Graph Rewrites☆25Nov 9, 2025Updated 9 months ago
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆20Nov 20, 2025Updated 8 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆91Apr 26, 2026Updated 3 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆73Aug 1, 2025Updated last year
- Allo Accelerator Design and Programming Framework (PLDI'24)☆402Updated this week
- Using e-graphs for logic synthesis (ICCAD'25)☆35Updated this week
- E-Graphs, natively in MLIR☆35Updated this week
- A Lean-embedded framework to verify Verilog modules☆15Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆18May 19, 2025Updated last year
- ☆17Mar 26, 2025Updated last year
- A compiler for lowering quantized ML models to AMD AI Engine (AIE) firmware.☆20Jul 31, 2026Updated last week
- pangenome alignment, implicit/explicit graph, and variants for human pangenome project release 2☆23Jul 1, 2026Updated last month
- isla coq infrastructure☆22Mar 11, 2025Updated last year
- Official codebase for the MLSys 2026 paper "IntAttention: A Fully Integer Attention Pipeline for Efficient Edge Inference". It enables hi…☆20May 29, 2026Updated 2 months ago
- A programming language for writing constraint-based integrated circuit layout generators☆17Jun 17, 2026Updated last month
- A standard for floating point accuracy benchmarks☆62Apr 9, 2026Updated 4 months ago
- Egraphs Modulo Theories☆20Jun 10, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Driving Snax with MLIR☆24Apr 22, 2026Updated 3 months ago
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆33Mar 28, 2026Updated 4 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ot-coq☆17Sep 5, 2023Updated 2 years ago
- ☆41Jul 28, 2026Updated last week
- ☆20Jan 2, 2026Updated 7 months ago