CLab-HKUST-GZ / micro58-axcoreLinks
☆30Updated 3 months ago
Alternatives and similar repositories for micro58-axcore
Users that are interested in micro58-axcore are comparing it to the libraries listed below
Sorting:
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆85Updated 9 months ago
- A co-design architecture on sparse attention☆55Updated 4 years ago
- ☆48Updated 4 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Updated last year
- ☆113Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆108Updated 9 months ago
- ☆26Updated 11 months ago
- ☆35Updated last month
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Updated 10 months ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆119Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 4 months ago
- EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator☆18Updated 7 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆82Updated 10 months ago
- ☆56Updated 2 months ago
- MICRO 2024 Evaluation Artifact for FuseMax☆16Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆46Updated last year
- The wafer-native AI accelerator simulation platform and inference engine.☆49Updated 3 weeks ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆24Updated last year
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆39Updated last year
- Research about dataflow architecture☆12Updated 2 years ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Updated last year
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆54Updated 6 months ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- ☆126Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆70Updated last month
- FSA: Fusing FlashAttention within a Single Systolic Array☆84Updated 5 months ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆126Updated 2 years ago