Alternatives and similar repositories for uvmprimer

Users that are interested in uvmprimer are comparing it to the libraries listed below

• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆282Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆434Updated 3 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆329Updated 3 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆261Updated 12 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆471Updated 5 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆468Updated this week
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆201Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆204Updated 5 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆182Updated 7 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆224Updated 2 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆387Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆834Updated 7 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,389Updated last week
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆146Updated 3 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆294Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆461Updated 4 months ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆273Updated 2 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆108Updated 9 months ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆128Updated 7 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆149Updated 7 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated last month
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆132Updated 4 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆155Updated 3 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆595Updated 6 months ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆109Updated 11 years ago