Alternatives and similar repositories for uvmprimer:

Users that are interested in uvmprimer are comparing it to the libraries listed below

• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆257Updated 2 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆285Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆413Updated 2 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆181Updated 7 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆378Updated 7 months ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆237Updated 11 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆403Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆182Updated 4 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆401Updated last month
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆145Updated 4 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆186Updated last year
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆162Updated 6 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,203Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆388Updated 5 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆776Updated 6 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆248Updated last week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆300Updated 9 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆116Updated 3 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆125Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆137Updated 6 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆233Updated last year
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆250Updated last year
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆99Updated last month
• svunit / svunit
  ☆195Updated last month
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆122Updated 2 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆124Updated 3 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆491Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆520Updated 2 weeks ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆348Updated 6 months ago