VHDL Code for infrastructural blocks (designed for FPGA)
☆15Oct 26, 2022Updated 3 years ago
Alternatives and similar repositories for openStreamHDL
Users that are interested in openStreamHDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated 2 months ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Sep 5, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆65Nov 7, 2025Updated 5 months ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Hardware Description Language Translator☆19Apr 20, 2026Updated last week
- Experiments with Cologne Chip's GateMate FPGA architecture☆18Nov 16, 2023Updated 2 years ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- VHDL related news.☆27Updated this week
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆17Apr 7, 2026Updated 3 weeks ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 2 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 2 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆189Mar 10, 2024Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆61Nov 14, 2025Updated 5 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆39Apr 13, 2026Updated 3 weeks ago
- Lightweight UART core in VHDL☆14Jan 18, 2025Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆28Jul 11, 2024Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆54Dec 6, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A JSON library implemented in VHDL.☆84Feb 8, 2026Updated 2 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- ☆33Apr 30, 2023Updated 3 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated last month
- Source code and schematics for CO monitor based on MQ-7 module that calculates CO ppm concentration☆18Mar 9, 2019Updated 7 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Mar 13, 2026Updated last month
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago