juliancoy / openStreamHDL
VHDL Code for infrastructural blocks (designed for FPGA)
☆14Updated 2 years ago
Alternatives and similar repositories for openStreamHDL:
Users that are interested in openStreamHDL are comparing it to the libraries listed below
- GUI editor for hardware description designs☆27Updated last year
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Generate symbols from HDL components/modules☆20Updated 2 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆12Updated 2 years ago
- Repository containing the DSP gateware cores☆12Updated 5 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Atom Hardware IDE☆13Updated 3 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- VHDL dependency analyzer☆23Updated 4 years ago
- Library of reusable VHDL components☆27Updated 11 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- An open-source VHDL library for FPGA design.☆31Updated 2 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 3 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆22Updated last week
- Virtual development board for HDL design☆40Updated last year
- USB virtual model in C++ for Verilog☆29Updated 4 months ago
- ☆20Updated 2 years ago
- simple hyperram controller☆11Updated 6 years ago
- A padring generator for ASICs☆25Updated last year
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated last year
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- Use ECP5 JTAG port to interact with user design☆26Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆28Updated last year
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago