Alternatives and similar repositories for riscv-isa-sim

Users that are interested in riscv-isa-sim are comparing it to the libraries listed below

• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆293Updated this week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆139Updated 6 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆185Updated 3 weeks ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆72Updated last month
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆125Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆173Updated 8 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆90Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆241Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆220Updated last week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 8 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 8 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated 2 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated 3 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆187Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆193Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆193Updated 8 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 3 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆241Updated 9 months ago