Alternatives and similar repositories for riscv-isa-sim:

Users that are interested in riscv-isa-sim are comparing it to the libraries listed below

• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆80Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆54Updated 3 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆116Updated 7 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆117Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆62Updated 11 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆98Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆92Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆149Updated this week
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆71Updated 3 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 2 weeks ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆91Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆200Updated last week
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆145Updated 10 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year