mflowgen / skywater-130nmLinks
ASIC Design kit for Skywater 130 for use with mflowgen
☆13Updated 2 years ago
Alternatives and similar repositories for skywater-130nm
Users that are interested in skywater-130nm are comparing it to the libraries listed below
Sorting:
- ☆20Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Updated 4 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- This is a python repo for flattening Verilog☆20Updated 3 weeks ago
- ☆29Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 7 months ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆20Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆29Updated 5 years ago
- A configurable SRAM generator☆56Updated 4 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated 3 weeks ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- This is a tutorial on standard digital design flow☆81Updated 4 years ago
- ☆36Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 8 months ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- CMake based hardware build system☆35Updated 3 weeks ago
- Hardware Formal Verification☆16Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago