Alternatives and similar repositories for skywater-130nm:

Users that are interested in skywater-130nm are comparing it to the libraries listed below

• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆31Updated 2 months ago
• efeslab / hardware-bugbase
  ☆17Updated 9 months ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 2 months ago
• pulp-platform / ELAU
  ☆13Updated 9 months ago
• sterin / super-prove-build
  ☆11Updated 4 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated last month
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 5 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆22Updated last year
• pulp-platform / svase
  ☆31Updated 2 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆51Updated 4 months ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆40Updated 2 weeks ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆51Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 2 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆27Updated 11 months ago