Alternatives and similar repositories for pulp-freertos

Users that are interested in pulp-freertos are comparing it to the libraries listed below

• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 weeks ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆26Updated 8 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• AlSaqr-platform / he-soc
  ☆32Updated last week
• b224hisl / rioschip
  ☆33Updated 3 years ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆24Updated 6 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆63Updated 10 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆39Updated 7 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated 2 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 6 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• litex-hub / zephyr-on-litex-vexriscv
  ☆15Updated 6 months ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 3 months ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆20Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆54Updated 4 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago