Alternatives and similar repositories for riscv-poky

Users that are interested in riscv-poky are comparing it to the libraries listed below

• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆71Updated 4 years ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 7 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆99Updated last year
• freebsd-riscv / freebsd
  FreeBSD src tree
  ☆18Updated 4 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 4 months ago
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆100Updated 3 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 8 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆150Updated 3 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆172Updated 9 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 10 months ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆333Updated last month
• riscvarchive / riscv-qemu
  QEMU with RISC-V (RV64G, RV32G) Emulation Support
  ☆388Updated 6 years ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆65Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• sifiveinc / riscv-linux
  RISC-V Linux Port
  ☆36Updated last week
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆34Updated 10 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆77Updated 6 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 2 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆64Updated 6 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 8 years ago
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆124Updated 4 years ago