Alternatives and similar repositories for riscv-poky

Users that are interested in riscv-poky are comparing it to the libraries listed below

• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 8 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆99Updated 3 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• riscvarchive / riscv-glibc
  RISC-V port of GNU's libc
  ☆71Updated 4 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆76Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 2 months ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• freebsd-riscv / freebsd
  FreeBSD src tree
  ☆18Updated 4 years ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated last year
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• lowRISC / rocket
  ☆32Updated 7 years ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆65Updated 5 years ago
• riscvarchive / riscv-wiki
  ☆250Updated 8 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 7 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆171Updated 9 years ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆52Updated 3 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 3 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 2 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 8 months ago