xobs / spibone
Wishbone bridge over SPI
☆11Updated 5 years ago
Alternatives and similar repositories for spibone:
Users that are interested in spibone are comparing it to the libraries listed below
- Simplified environment for litex☆14Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- My pergola FPGA projects☆30Updated 3 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- Cross compile FPGA tools☆22Updated 4 years ago
- ☆12Updated 3 years ago
- verilog core for ws2812 leds☆32Updated 3 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- SD device emulator from ProjectVault☆15Updated 5 years ago
- There are many RISC V projects on iCE40. This one is mine.☆14Updated 4 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆30Updated 3 years ago
- Project Trellis database☆13Updated last year
- Open source hardware down to the chip level!☆30Updated 3 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- DVI video out example for prjtrellis☆16Updated 6 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- Finding the bacteria in rotting FPGA designs.☆13Updated 4 years ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- ☆63Updated 4 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆12Updated 9 months ago
- Dual MikroBUS board for Upduino 2 FPGA☆18Updated 6 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆17Updated 10 months ago
- Yet Another Debug Transport☆20Updated 2 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated 9 months ago
- DSP Blocks for the nMigen (Python) Toolbox☆10Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago