Alternatives and similar repositories for abicop:

Users that are interested in abicop are comparing it to the libraries listed below

• riscvarchive / riscv-lld
  RISC-V port of LLVM Linker
  ☆24Updated 6 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆47Updated 7 years ago
• SNSystems / dexter
  DExTer - Debug Experience Tester
  ☆33Updated 3 years ago
• TUD-OS / NUL
  NOVA userland
  ☆48Updated 11 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• google / minetest_pnr
  Place & Router for Minetest
  ☆18Updated 2 years ago
• burtonsamograd / anser
  A header only Boolean Propagator Network framework for the omni-directional computation of Integer mathematical functions and computation…
  ☆14Updated 6 years ago
• XVilka / cparse
  Parser of C-syntax data definitions, C-syntax function definitions
  ☆20Updated 12 years ago
• stephenrkell / donald
  The Mickey Mouse of dynamic linkers
  ☆14Updated 2 months ago
• ARM-software / asl-interpreter
  Example implementation of Arm's Architecture Specification Language (ASL)
  ☆115Updated 5 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆50Updated this week
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• Arcterus / lejit
  A simple JIT library in Rust
  ☆19Updated 10 years ago
• xiangzhai / dragonegg
  DragonEgg has been migrated to GCC 8 and LLVM 6 but also able to work for GCC 4.8 and LLVM 3.3
  ☆18Updated 5 years ago
• stephank / rvsim
  A RISC-V simulator implementing RV32G[C].
  ☆34Updated 2 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆77Updated last week
• embecosm / gso2
  GNU Superoptimizer Version 2
  ☆26Updated 3 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• michaeljclark / riscv-meta
  RISC-V Instruction Set Metadata
  ☆41Updated 6 years ago
• pmachata / dwgrep
  a tool for querying Dwarf (debuginfo) graphs
  ☆53Updated 9 months ago
• allvm / allvm-tools
  ALLVM Tools
  ☆56Updated 2 years ago
• codeplaysoftware / lldb-msp430
  Codeplay's tutorial LLDB-MSP430 - as presented at the 2016 EuroLLVM Developers' Meeting in Barcelona.
  ☆10Updated 8 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆34Updated 3 years ago
• whitequark / Boneless-CPU
  Resource-efficient 16-bit CPU architecture for FPGA control plane
  ☆93Updated 2 weeks ago
• AveryOS / avery
  x86-64 kernel in Rust
  ☆31Updated 8 years ago
• riscvarchive / riscv-poky
  Port of the Yocto Project to the RISC-V ISA
  ☆62Updated 6 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 7 years ago