lowRISC / abicop
Work towards a "golden model" of the RISC-V calling convention(s)
☆10Updated 7 years ago
Alternatives and similar repositories for abicop:
Users that are interested in abicop are comparing it to the libraries listed below
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- RISC-V port of LLVM Linker☆24Updated 6 years ago
- NOVA userland☆48Updated 11 years ago
- GNU Superoptimizer Version 2☆26Updated 3 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- NOVA runtime environment (official branch)☆34Updated 3 years ago
- A clang wrapper for musl C library. Pretty hacky, I know.☆34Updated 10 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Reverse Engineering of NVIDIA's Tegra driver for Linux☆34Updated 7 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Updated 5 years ago
- A collection of little open source FPGA hobby projects☆48Updated 5 years ago
- DExTer - Debug Experience Tester☆33Updated 3 years ago
- A header only Boolean Propagator Network framework for the omni-directional computation of Integer mathematical functions and computation…☆14Updated 6 years ago
- RISC-V Instruction Set Metadata☆41Updated 6 years ago
- L3 based MIPS specification and emulator☆15Updated 3 years ago
- chipy hdl☆17Updated 7 years ago
- ☆19Updated 5 years ago
- the actual epiphany backend☆20Updated 11 years ago
- a simple C-to-Verilog compiler☆48Updated 8 years ago
- DragonEgg has been migrated to GCC 8 and LLVM 6 but also able to work for GCC 4.8 and LLVM 3.3☆19Updated 6 years ago
- Port of the Yocto Project to the RISC-V ISA☆62Updated 6 years ago
- A collection of shader compiler bugs.☆49Updated 7 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- a tool for querying Dwarf (debuginfo) graphs☆55Updated 11 months ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆96Updated 2 months ago
- Code which loads custom ISA on Intel Haswell GPUs☆47Updated 8 years ago
- small experiment to learn some rust via a nRF24 Enhanced Shockburst receiver (2SPS IQ -> packets)☆12Updated 4 years ago
- RISC-V user-mode emulator that runs DooM☆53Updated 6 years ago