Alternatives and similar repositories for GDS3D:

Users that are interested in GDS3D are comparing it to the libraries listed below

• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆117Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 4 months ago
• trilomix / GDS3D
  GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …
  ☆211Updated 6 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆60Updated 2 weeks ago
• cdsdm / cdsdm
  Cadence Virtuoso Design Management System
  ☆33Updated 2 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆113Updated last week
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆46Updated 2 years ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆42Updated 7 months ago
• ananthchellappa / SKILL
  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.
  ☆41Updated 3 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 6 months ago
• ncsu-eda / FreePDK3
  ☆132Updated 3 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆56Updated 3 months ago
• idea-fasoc / fasoc
  ☆53Updated last year
• laurentc2 / Verilog2Spice
  Simple strutured VERILOG netlist to SPICE netlist translator
  ☆22Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆48Updated 9 months ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆55Updated 4 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆52Updated last week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆160Updated 4 years ago
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆21Updated 4 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆38Updated 5 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆64Updated last month
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆47Updated 2 years ago
• ABKGroup / PROBE3.0
  ☆37Updated 10 months ago
• parallaxsw / OpenSTA
  ☆56Updated this week
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆39Updated last year
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆37Updated last year
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago