rewrite subset of linux 2.6 by OOP, C++ advanced topics
☆10Jul 22, 2021Updated 4 years ago
Alternatives and similar repositories for startos
Users that are interested in startos are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 3 years ago
- ☆13Jul 26, 2021Updated 4 years ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Jun 3, 2022Updated 3 years ago
- Let's write an OS which can run on ARM in Rust from scratch! (🚧WIP)☆17Mar 13, 2022Updated 4 years ago
- ☆12Jan 22, 2026Updated 2 months ago
- A virtio layer for xv6☆12Apr 16, 2019Updated 6 years ago
- 项目的主仓库☆26Sep 11, 2022Updated 3 years ago
- ☆13Mar 15, 2026Updated last week
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Jul 20, 2023Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- hypercraft is a VMM library written in Rust.☆54Oct 20, 2024Updated last year
- [New Version] This is FAT32 FileSystem Library, which is #![no_std] and does not use alloc.☆31Oct 6, 2021Updated 4 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Dec 25, 2020Updated 5 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- My tests and experiments with some popular dl frameworks.☆17Sep 11, 2025Updated 6 months ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- ☆14Dec 15, 2022Updated 3 years ago
- [WIP] Xv6, a simple Unix-like teaching operating system, re-implemented for ARMv8 (AArch64), written in C☆17Apr 25, 2021Updated 4 years ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated 2 years ago
- This is DreamOS C Version by lizhirui since 2021-05-18☆10Aug 23, 2021Updated 4 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆14Aug 7, 2022Updated 3 years ago
- a compiler for CSC-Compiler-2022☆13Aug 22, 2022Updated 3 years ago
- A Micro Kernel Operating System☆12Nov 23, 2019Updated 6 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18May 15, 2022Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆25Mar 8, 2026Updated 2 weeks ago
- This is an example of RSA encrypt/decrypt methods running on OP-TEE.☆11Sep 6, 2018Updated 7 years ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 4 years ago
- 《深入理解文件系统原理和实 践》pdf, ISBN: 978-7-89381-214-9☆27May 6, 2024Updated last year
- 自嗨虚拟化软件 - 'Enjoy yourself' type-1 hypervisor software☆25Apr 21, 2022Updated 3 years ago
- A small RISC-V kernel coding by C, tested on sifive unmatched board.☆16Aug 20, 2022Updated 3 years ago
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- 《计算机设计与实践》测试框架☆17Jun 28, 2022Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- ☆17Mar 17, 2022Updated 4 years ago
- Course website for Advanced Operating Systems☆13Apr 8, 2022Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- A Small RISC-V Virtual Machine☆94Mar 16, 2022Updated 4 years ago