Alternatives and similar repositories for gem5_data_proc

Users that are interested in gem5_data_proc are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆115Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 3 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆37Updated 3 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• dhschall / gem5-fdp
  Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
  ☆28Updated this week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆74Updated last week
• hpsresearchgroup / scarab
  Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator
  ☆81Updated 3 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• eric-rotenberg / CVP
  Championship Value Prediction (CVP) simulator.
  ☆17Updated 4 years ago
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• JamesAslan / MicroArchBench
  ☆75Updated last year
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆27Updated 2 years ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆43Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• pranith / qpoints
  Qemu tracing plugin using SimPoints
  ☆17Updated last year
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• PrincetonUniversity / gem5_FDIP
  ☆12Updated last year
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 3 months ago
• Shuiliusheng / gem5_riscv_ckpt
  small and independent checkpoint
  ☆12Updated 2 years ago
• zeal4u / PMP
  About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.
  ☆14Updated 2 years ago
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆34Updated 5 years ago
• OSCPU / ysyxSoC
  ☆89Updated 2 months ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆124Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆73Updated last week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year