Alternatives and similar repositories for jtag-remote-server

Users that are interested in jtag-remote-server are comparing it to the libraries listed below

• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆23Updated 2 years ago
• chili-chips-ba / wireguard-fpga
  Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…
  ☆106Updated last month
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆63Updated 3 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 5 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• j-marjanovic / chisel-stuff
  Various examples for Chisel HDL
  ☆30Updated 3 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• anishathalye / bin2coe
  A tool to convert binary files to COE files 💫
  ☆16Updated 2 months ago
• cnrv / OSEDA
  Open-Source EDA workshop for RISC-V community
  ☆12Updated 3 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 6 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆19Updated 8 months ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆41Updated last week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated 9 months ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated 11 months ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated last year
• asinghani / crypto-accelerator-chip
  Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…
  ☆22Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆87Updated last month
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆31Updated 5 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆47Updated 7 months ago
• rgwan / bapi-rv32i
  A extremely size-optimized RV32I soft processor for FPGA.
  ☆28Updated 7 years ago
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆60Updated 2 weeks ago
• sipeed / TangMega-138KPro-example
  Tang Mega 138K Pro examples
  ☆76Updated 2 weeks ago