Alternatives and similar repositories for Toooba:

Users that are interested in Toooba are comparing it to the libraries listed below

• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆35Updated 3 weeks ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated last week
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated 2 weeks ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 4 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆46Updated 10 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated 3 weeks ago
• CTSRD-CHERI / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆11Updated 11 months ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆23Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆52Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆35Updated 3 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆100Updated last week
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆26Updated 4 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 2 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆31Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆56Updated last week
• hex-five / multizone-fpga
  This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…
  ☆29Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated this week