ahmedshahein / DSP-RTL-Lib
RTL Verilog library for various DSP modules
☆86Updated 3 years ago
Alternatives and similar repositories for DSP-RTL-Lib:
Users that are interested in DSP-RTL-Lib are comparing it to the libraries listed below
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆55Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- SDRAM controller with AXI4 interface☆91Updated 5 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆68Updated last year
- ☆36Updated 9 years ago
- AHB3-Lite Interconnect☆88Updated 11 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- This is the repository for the IEEE version of the book☆58Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- APB to I2C☆40Updated 10 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- round robin arbiter☆72Updated 10 years ago