comparch-security / spike-cache
Spike with a coherence supported cache model
☆13Updated 8 months ago
Alternatives and similar repositories for spike-cache:
Users that are interested in spike-cache are comparing it to the libraries listed below
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week
- ☆20Updated last year
- Gem5 with PCI Express integrated.☆16Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆41Updated 3 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- ☆12Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- ☆53Updated 4 years ago
- Championship Value Prediction (CVP) simulator.☆16Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆29Updated 5 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- gem5 repository to study chiplet-based systems☆70Updated 5 years ago
- ☆22Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆35Updated 5 months ago
- Original test vector of RISC-V Vector Extension☆11Updated 4 years ago
- ☆15Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- ☆91Updated last year
- RISC-V Matrix Specification☆19Updated 3 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- The OpenPiton Platform☆28Updated last year