Spike with a coherence supported cache model
☆14Jul 9, 2024Updated last year
Alternatives and similar repositories for spike-cache
Users that are interested in spike-cache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Apr 22, 2026Updated last week
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Mar 10, 2026Updated last month
- QARMA block cipher in C☆31Sep 10, 2022Updated 3 years ago
- Implementation of Tagged Memory security policies into Rocket Core☆10Nov 8, 2016Updated 9 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- PalanTír: Optimizing Attack Provenance with Hardware-enhanced System Observability, ACM CCS'22☆24Nov 11, 2024Updated last year
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- ☆34Nov 7, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆14Jun 7, 2021Updated 4 years ago
- ☆35Jul 23, 2023Updated 2 years ago
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last month
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆12Jan 18, 2016Updated 10 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆12Oct 14, 2021Updated 4 years ago
- Roll the dice, in elixir☆14Dec 13, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP.☆12Apr 27, 2024Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 4 months ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.☆11Apr 27, 2024Updated 2 years ago
- BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…☆19Oct 9, 2020Updated 5 years ago
- Andes OpenEmbedded (OE) BSP Layer☆16Apr 14, 2026Updated 2 weeks ago
- Very basic implementation of SPM for gem5 simulator (legacy gem5 version)☆12Feb 18, 2020Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Jun 1, 2021Updated 4 years ago
- RISC-V SST CPU Component☆24Apr 15, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆38Mar 26, 2024Updated 2 years ago
- New batched algorithm for sparse matrix-matrix multiplication (SpMM)☆16May 7, 2019Updated 6 years ago
- 乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四☆20Aug 20, 2024Updated last year
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆37Apr 15, 2026Updated 2 weeks ago
- ☆89Apr 10, 2026Updated 2 weeks ago
- Nebula: Deep Neural Network Benchmarks in C++☆13Jan 2, 2025Updated last year