comparch-security / spike-cacheLinks
Spike with a coherence supported cache model
☆13Updated 11 months ago
Alternatives and similar repositories for spike-cache
Users that are interested in spike-cache are comparing it to the libraries listed below
Sorting:
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- RISC-V Matrix Specification☆22Updated 6 months ago
- ☆31Updated 2 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- ☆91Updated last year
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 9 months ago
- upstream: https://github.com/RALC88/gem5☆31Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated last week
- ☆41Updated 5 months ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆14Updated 2 years ago
- ☆15Updated 9 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆102Updated 2 years ago
- ☆11Updated last month