stffrdhrn / uartLinks
Verilog uart receiver and transmitter modules for De0 Nano
☆18Updated 10 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below
Sorting:
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated 10 months ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆30Updated 5 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- FT2232HL JTAG & UART Downloader☆19Updated 4 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆19Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Repository and Wiki for Chip Hack events.☆51Updated 4 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- HDMI + GPU-pipeline + FFT☆14Updated 9 years ago
- IP submodules, formatted for easier CI integration☆30Updated 2 months ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆17Updated 3 years ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- Wishbone controlled I2C controllers☆52Updated 10 months ago
- Small footprint and configurable Inter-Chip communication cores☆61Updated 2 months ago
- USB Full Speed PHY☆46Updated 5 years ago
- USB capture IP☆21Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 6 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 6 months ago
- ☆61Updated 4 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Various projects of SPI loader module for xilinx fpga☆33Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 3 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Updated 8 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year