Alternatives and similar repositories for uart

Users that are interested in uart are comparing it to the libraries listed below

• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆19Updated last year
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆31Updated 5 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆55Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated 2 months ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆23Updated 5 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆43Updated 6 years ago
• tomverbeure / usb_system
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆24Updated last month
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆31Updated 5 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆30Updated 5 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆36Updated this week
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated last month
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• regymm / ymmcu-ft2232
  FT2232HL JTAG & UART Downloader
  ☆20Updated 4 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆18Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated this week
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆34Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 7 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 4 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 4 years ago
• ZipCPU / wbpwmaudio
  A wishbone controlled PWM (audio) controller
  ☆18Updated last year