maswx / vu13p_corundumLinks
corundum work on vu13p
☆22Updated 2 years ago
Alternatives and similar repositories for vu13p_corundum
Users that are interested in vu13p_corundum are comparing it to the libraries listed below
Sorting:
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆23Updated 10 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆22Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆40Updated 8 months ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆36Updated 4 years ago
- ☆17Updated 2 months ago
- Distributed Accelerator OS☆63Updated 3 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- SmartNIC☆14Updated 6 years ago
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆104Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 6 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆28Updated 6 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- ☆29Updated 8 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- ☆14Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago