maswx / vu13p_corundum
corundum work on vu13p
☆19Updated last year
Alternatives and similar repositories for vu13p_corundum
Users that are interested in vu13p_corundum are comparing it to the libraries listed below
Sorting:
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆19Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆11Updated last year
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆23Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 3 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆14Updated 10 years ago
- Wraps the NVDLA project for Chipyard integration☆20Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Verilog PCI express components☆22Updated last year
- ☆14Updated 2 years ago
- Ethernet switch implementation written in Verilog☆47Updated last year
- Computational Storage Device based on the open source project OpenSSD.☆23Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 4 months ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆28Updated 9 months ago
- ☆27Updated 4 years ago
- ☆25Updated last year
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆10Updated 3 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- ☆12Updated 8 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆15Updated 5 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago