maswx / vu13p_corundumLinks
corundum work on vu13p
☆19Updated last year
Alternatives and similar repositories for vu13p_corundum
Users that are interested in vu13p_corundum are comparing it to the libraries listed below
Sorting:
- Ethernet switch implementation written in Verilog☆49Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- ☆15Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆15Updated 9 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- understanding of cocotb (In Chinese Only)☆17Updated last week
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Updated 4 years ago
- ☆26Updated last year
- ☆59Updated 4 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆14Updated 11 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- ☆27Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- PCI Express controller model☆57Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated last month
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆28Updated 11 months ago
- ☆16Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆28Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- ☆30Updated 2 months ago