Alternatives and similar repositories for pdmmic-example:

Users that are interested in pdmmic-example are comparing it to the libraries listed below

• kazkojima / pcm2pdm-example
  A tiny example of PCM to PDM pipeline on FPGA
  ☆19Updated 3 years ago
• dineshannayya / usb1_host
  USB1.1 Host Controller + PHY
  ☆14Updated 3 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆32Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆28Updated 8 years ago
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆17Updated 2 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 11 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆25Updated 3 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• Martoni / spi2wb
  Drive a Wishbone master bus with an SPI bus.
  ☆10Updated 4 months ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆38Updated 4 years ago
• PulseRain / PulseRain_FP51_MCU
  PulseRain FP51 MCU, with peripherals
  ☆14Updated 7 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆21Updated 10 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆37Updated 3 years ago
• skristiansson / i2s
  i2s core, with support for both transmit and receive
  ☆29Updated 6 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆26Updated 4 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆14Updated 7 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆41Updated 4 years ago