Alternatives and similar repositories for DDR2_Controller:

Users that are interested in DDR2_Controller are comparing it to the libraries listed below

• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆100Updated 2 months ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆138Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆96Updated 3 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆126Updated 6 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆83Updated 8 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆119Updated 3 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆56Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆61Updated last year
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆67Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆85Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆137Updated last month
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆85Updated 10 months ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆85Updated last year
• freecores / apbi2c
  APB to I2C
  ☆39Updated 10 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆111Updated 7 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆145Updated 2 weeks ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆53Updated 10 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆192Updated last year