Alternatives and similar repositories for DDR2_Controller

Users that are interested in DDR2_Controller are comparing it to the libraries listed below

• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆97Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆79Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆62Updated 4 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆65Updated 2 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆92Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆120Updated 11 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆88Updated 8 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆64Updated last year
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆52Updated 4 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 4 years ago
• shubhi704 / APB-Protocol
  ☆47Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 6 months ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆115Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆72Updated 6 years ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆117Updated 6 months ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆130Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆174Updated 2 weeks ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆141Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆148Updated 7 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆55Updated 5 years ago