☆80Feb 4, 2021Updated 5 years ago
Alternatives and similar repositories for DDR4_controller
Users that are interested in DDR4_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆94Feb 28, 2018Updated 8 years ago
- DDR4 Simulation Project in System Verilog☆46Aug 18, 2014Updated 11 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆600Oct 10, 2021Updated 4 years ago
- ☆14Feb 24, 2025Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆130Jul 22, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- openHMC - an open source Hybrid Memory Cube Controller☆51Apr 27, 2016Updated 10 years ago
- General Purpose AXI Direct Memory Access☆67May 12, 2024Updated 2 years ago
- ☆15Jul 28, 2022Updated 3 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- The memory model was leveraged from micron.☆31Mar 24, 2018Updated 8 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- Implementation of the PCIe physical layer☆63Jul 11, 2025Updated 10 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- ☆29May 11, 2021Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆26Feb 16, 2022Updated 4 years ago
- DDR2 memory controller written in Verilog☆83Feb 28, 2012Updated 14 years ago
- Network on Chip for MPSoC☆28May 20, 2026Updated 2 weeks ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆368May 29, 2026Updated last week
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆83Mar 21, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆65Dec 15, 2025Updated 5 months ago
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆44Dec 11, 2025Updated 5 months ago
- ☆92Apr 10, 2026Updated last month
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 5 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆88Oct 6, 2022Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 7 years ago
- TCP/IP and UDP/IP protocol stack off-loading☆19Aug 9, 2020Updated 5 years ago
- Small footprint and configurable DRAM core☆505Jun 2, 2026Updated last week
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆23Dec 17, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆46Jul 28, 2017Updated 8 years ago
- ☆36Jun 4, 2024Updated 2 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 6 years ago
- UCSD CSE240A Project: Branch Predictor☆11Jul 24, 2017Updated 8 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- Opensource DDR3 Controller☆446May 21, 2026Updated 2 weeks ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 10 years ago