☆83Feb 4, 2021Updated 5 years ago
Alternatives and similar repositories for DDR4_controller
Users that are interested in DDR4_controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆98Feb 28, 2018Updated 8 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆642Oct 10, 2021Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 12 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆148Jul 22, 2021Updated 5 years ago
- ☆16Jul 16, 2026Updated 3 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆54Apr 27, 2016Updated 10 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆16Sep 24, 2020Updated 6 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- Small footprint and configurable DRAM core☆568Updated this week
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Opensource DDR3 Controller☆497Sep 12, 2026Updated last month
- General Purpose AXI Direct Memory Access☆82May 12, 2024Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆407Oct 23, 2026Updated last week
- The memory model was leveraged from micron.☆32Mar 24, 2018Updated 8 years ago
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆56Dec 11, 2025Updated 10 months ago
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 3 years ago
- ☆26Oct 14, 2026Updated 2 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆159Mar 19, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆94Apr 8, 2024Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆90Oct 6, 2022Updated 4 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- A simple DDR3 memory controller☆68Aug 20, 2026Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆27Feb 16, 2022Updated 4 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆41Jun 10, 2026Updated 4 months ago
- SHA-256 cipher algorithm implementation☆13Jun 22, 2025Updated last year
- ☆30May 11, 2021Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆93Mar 21, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 10 years ago
- UVM resource from github, run simulation use YASAsim flow☆34Apr 25, 2020Updated 6 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 12 years ago
- Verilog PCI express components☆1,677Apr 26, 2024Updated 2 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- Network on Chip for MPSoC☆30Oct 19, 2026Updated last week