oprecomp / DDR4_controllerLinks
☆64Updated 4 years ago
Alternatives and similar repositories for DDR4_controller
Users that are interested in DDR4_controller are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- Verilog Content Addressable Memory Module☆110Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- round robin arbiter☆75Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- PCI Express controller model☆65Updated 2 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- ☆76Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- ☆78Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆174Updated last week
- ☆61Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Simple single-port AXI memory interface☆45Updated last year
- Pure digital components of a UCIe controller☆67Updated 2 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- BlackParrot on Zynq☆46Updated 6 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- NVMe Controller featuring Hardware Acceleration☆93Updated 4 years ago