oprecomp / DDR4_controllerLinks
☆67Updated 4 years ago
Alternatives and similar repositories for DDR4_controller
Users that are interested in DDR4_controller are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆114Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- round robin arbiter☆75Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- ☆78Updated 11 years ago
- BlackParrot on Zynq☆48Updated 2 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- NVMe Controller featuring Hardware Acceleration☆94Updated 4 years ago
- ☆64Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated last week
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- ☆79Updated 3 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆176Updated last month
- PCI Express controller model☆68Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago